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#11
Quote from: vasilisk on Yesterday at 18:49With careful observation it is easy to solve...
I love that the final puzzle has more than one clue on how to solve it. (You can get it via the name or via the numbers)
#12
General Discussion - Introductions / Re: Why did you choose the CPC...
Last post by Gryzor - Today at 09:33Similar story to @VincentGR 's. Saw a 2600 at a cousin's home. My jaw dropped when I realised you could control what happened on-screen. Simply an unimaginable concept. Didn't say much about it though, yet my parents did take note.
...and decided to get me a computer instead, bless them. I bet the 464 was their choice both because of the seller at the store (which was the Amstrad distributor
) AND because it came with a screen.
...and decided to get me a computer instead, bless them. I bet the 464 was their choice both because of the seller at the store (which was the Amstrad distributor
) AND because it came with a screen. #13
@lmimmfn
During M1, on which clock edge would you grab data from the data line on the first one, on the second one, or on another one?
On which clock edge would you retrieve data when Z80 reading from IO?
Will these be the same edge numbers if GA adds a WAIT signal?
These are detailed dilemmas.
During M1, on which clock edge would you grab data from the data line on the first one, on the second one, or on another one?
On which clock edge would you retrieve data when Z80 reading from IO?
Will these be the same edge numbers if GA adds a WAIT signal?
These are detailed dilemmas.
#14
All these animations are awesome, I wonder how many frames they are each using. E.g. when the skeleton is dying (disappearing as a cloud with a skull face inside) etc.
#15
I'm proud to announce that the 3rd and final volume of Learn Multiplatform Assembly with ChibiAkumas is out now!
Volume 3 is in the same format as volumes 1 and 2.
The first chapter is the assembly introduction which is basically the same as Volumes 1+2 (So you can read Volume 3 without having read the other volumes)
Volume 3 covers MIPS, TMS9900, SuperH, IBM370 and PowerPC CPUs
The book is around 50 pages longer than the previous volumes, so the price is slightly higher due to printing costs - In many countries I'm actually making slightly less money on this book.
The book is out now in B4 sized Hardback and A5 sized paperback...
Get the A5 Paperback Here: https://amzn.to/3y4hAfP
Get the B4 Hardback Here: https://amzn.to/3woRgwL
Large Print A4 paperback is also available Here: https://amzn.to/44wfTnW
Due to piracy problems and relatively low sales of Vol 2, I'm not planning to offer a Kindle version this time (I'm pretty sure there's bot scripts automatically ripping off the new releases), however I will be offering 'Buyers remorse' PDFs, I will post an update about this in the next couple of months once the dust has settled from the book release.
If you've not seen Volumes 1 or 2 yet, you can get them here:
Volume 1 covers Z80, 6502, 68000, 8086 and ARM CPUs: https://amzn.to/4dkBLXo
Volume 2 covers ARM Thumb, 65816, 6809, PDP-11 and Risc-V CPUs: https://amzn.to/3QmZITO
Volume 3 is in the same format as volumes 1 and 2.
The first chapter is the assembly introduction which is basically the same as Volumes 1+2 (So you can read Volume 3 without having read the other volumes)
Volume 3 covers MIPS, TMS9900, SuperH, IBM370 and PowerPC CPUs
The book is around 50 pages longer than the previous volumes, so the price is slightly higher due to printing costs - In many countries I'm actually making slightly less money on this book.
The book is out now in B4 sized Hardback and A5 sized paperback...
Get the A5 Paperback Here: https://amzn.to/3y4hAfP
Get the B4 Hardback Here: https://amzn.to/3woRgwL
Large Print A4 paperback is also available Here: https://amzn.to/44wfTnW
Due to piracy problems and relatively low sales of Vol 2, I'm not planning to offer a Kindle version this time (I'm pretty sure there's bot scripts automatically ripping off the new releases), however I will be offering 'Buyers remorse' PDFs, I will post an update about this in the next couple of months once the dust has settled from the book release.
If you've not seen Volumes 1 or 2 yet, you can get them here:
Volume 1 covers Z80, 6502, 68000, 8086 and ARM CPUs: https://amzn.to/4dkBLXo
Volume 2 covers ARM Thumb, 65816, 6809, PDP-11 and Risc-V CPUs: https://amzn.to/3QmZITO
#16
Applications (CPC and CPC-related) / Re: CubeMDOS / FAT16+FAT32-OS ...
Last post by Ast - Today at 08:49This piece of code is also used in iMPdos, i confirm !
#17
#18
General Discussion - Introductions / Re: Memorable CPC game intros ...
Last post by XeNoMoRPH - Today at 06:16 #19
Quote from: SerErris on Yesterday at 22:47I'm not sure I understand, no ROM on 8bit or 16bit computers are encrypted or scrambled? (well not that I heard of from C64, Amstrad, Speccy, Amiga or Atari ST).Quote from: Longshot on Yesterday at 13:17What is this project you are currently working on regarding Vortex?I do need to reverse envineer the ROM that is actually scrambled utilizing the M1 line. So depending on the M1 cycle it does scramble (actually descramble) or does not descramble the ROM. So if you read the ROM just normally (dump it, or read it with CPC) you will get all databytes scrambled and it is unusable.
I like to preserve it and get the unscrambled version (and commented source code).
So the way I now try to fill the remaining holes is, to sniff all rom reads with a Raspberry Pi PICO.
I have worked the last weekend on the code, which now looks ready (it does what I want it to do), and I can now hook up a CPC to this thing and start sniffing.
If you are interested in more detail, I could explain it, but probably not in this thread :-)
A dump of the CPC ROM should be directly executable via calls to same, i.e. can take hex from ROM and directky decompile without issue, unless I'm misunderstanding what you say?
#20
Quote from: Longshot on Yesterday at 13:17@SerErris :
I think I have accurately specified the number of the T cycle in an M cycle but I did not go into detail about the M cycles of the Z80A (I use the same references)
I also explain that the Opcode Fetch is done during M1 a little before when I describe the opcode fetch.
The cycle indicated TW in the IO REQ is the 3rd of cycle T of cycle M, even if T3 in the nomenclature is the 4th.
Even if the objective of the document is not to further describe the internal workings of the Z80A, I thank you for the precision and I have clarified the cycle number M
It is now much clearer in the english version. Thanks for the add.
However in Section 4.4.4 there is now this in the wording:
QuoteA cycle M consists of several T cycles, one of which has the particularity of taking into account the signal sent to the Wait pin by an external component. This wait cycle is commonly named Tw. At this Tw cycle it honors an active High signal and runs Wait cycles until this line getting down again.
It is actually a active low signal. /WAIT and it is working exactly the opposite way. So if it is low, the CPU will run wait cycles and if it is getting high again, the CPU will continue.
It is a little bit confusing as the Signal from the GA is called READY (active High). But that is aligned as READY is the opposite of /WAIT. So the Gatearray pulls the line high (actually a pull up does that) and the CPU can run. It pulls it low and the CPU will wait. The GA actually keeps this line low for 66% of the M cycle and only 33% it is high. That will lead to the synchronization we all know about.
So the sentence should read:
QuoteA cycle M consists of several T cycles, one of which has the particularity of taking into account the signal sent to the /WAIT pin by an external component. This wait cycle is commonly named Tw. At this Tw cycle it honors an active low signal on /WAIT and runs wait cycles until this line getting up again.