Changes
/* Half Cycles */
Unlike most microprocessors, the 6502 does not make memory accesses on an "as needed" basis. It always does a fetch or store on every single clock cycle. When there isn't anything to be fetched or stored, a "garbage" fetch or store occurs. This is mainly of importance with the memory-mapped I/O devices:
* When On NMOS, when adding a carry to the MSB of an address, a fetch occurs at a garbage address. The On CMOS chips refetch , the last byte of the instructionis refetched.* When On NMOS, when doing a fetch-modify-store instruction (INC, DEC, ASL, LSR, ROL, ROR), garbage is stored into the location during the "modify" cycle... followed by the "real" store cycle which stores the correct data. The On CMOS chips do , a second fetch is performed instead of a garbage store.
<br>
