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/* Interrupts */
On an IRQ, the CPU does the same as in the NMI case, but uses the vector at $FFFE/$FFFF.
On a BRK instruction, the CPU does the same as in the IRQ case, but sets bit4 (bBF flag) in the copy of the status register that is saved on the stack.
The priority sequence for interrupts, from top priority to bottom, is as follows: RESET, BRK, NMI, IRQ. [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf Source at chapter 7.19]
