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/* Block Diagrams */
=== Detailed view ===
[[File:CPU 6502 Detailed Block Diagram.jpg|500px]]
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== The Decode ROM (PLA) ==
The instruction register, which holds the opcode, and the current clock cycle within the instruction (T0 to T6) get fed into a 130×21 bit decode ROM, i.e. a ROM with 130 lines of 21 bits each.
While some other CPUs from the same era used microcode to interpret the instruction, the 6502 had this 130×21 bit PLA. All lines of the PLA compare the instruction and the current clock cycle, and if they match, the line fires. [https://www.pagetable.com/?p=39 Source]
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