* LD A,I and LD A,R normally copy the state of IFF2 to the Parity flag. NMOS Z80 suffers a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. [https://sinclair.wiki.zxnet.co.uk/wiki/Z80#LD_A,I_and_LD_A,R_bug Source]
* Although not mentioned in Zilog documentation, the Z80 CPU supports two types of reset: normal and special. A normal reset disables the maskable interrupt, selects interrupt mode 0, zeroes registers I & R and zeroes the program counter (PC). A special reset zeroes PC only. Furthermore, a hardware bug was discovered when the special reset occurs after a HALT instruction. [https://github.com/redcode/Z80/wiki/Z80-Special-Reset Source]
* Almost all Z80 inputs are sampled on a rising clock, but the /WAIT signal is sampled on a falling clock. [https://emulation.gametechwiki.com/index.php/Emulation_accuracy#Subcycle_accuracy Source]
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