Changes
Z80
,/* Load group */
{| class="wikitable" style="white-space: nowrap;"
|-
! Instruction !! Opcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| ld r,r̃ || 01rrrr̃r̃r̃ || 1 || 4 (4) || M1 || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || r := r̃ ||rowspan=15|8-bit Load
|-
| ld (hl),r || 01110rrr || 2 || 7 (4,3) || M1, MW || (hl) := r
|-
| ld r,(hl) || 01rrr110 || 2 || 7 (4,3) || M1, MR || r := (hl)
|-
| ld s,s̃ || DD/FD 01ssss̃s̃s̃ || 2 || 8 (4,4) || M1, M1 || s := s̃
|-
| ld (ixy+d),r || DD/FD 01110rrr dddddddd || 5 || 19 (4,4,3,5,3) || M1, M1, MR, INT(5), MW || (ixy+d) := r
|-
| ld r,(ixy+d) || DD/FD 01rrr110 dddddddd || 5 || 19 (4,4,3,5,3) || M1, M1, MR, INT(5), MR || r := (ixy+d)
|-
| ld r,n || 00rrr110 nnnnnnnn || 2 || 7 (4,3) || M1, MR || r := n
|-
| ld (hl),n || 00110110 nnnnnnnn || 3 || 10 (4,3,3) || M1, MR, MW || (hl) := n
|-
| ld (ixy+d),n || DD/FD 00110110 dddddddd nnnnnnnn || 6 || 19 (4,4,3,52,3,3) || M1, M1, MR, INT(2), MR, MW || (ixy+d) := n
|-
| ld (bc),a || 00000010 || 2 || 7 (4,3) || M1, MW || (bc) := a
|-
| ld a,(bc) || 00001010 || 2 || 7 (4,3) || M1, MR || a := (bc)
|-
| ld (de),a || 00010010 || 2 || 7 (4,3) || M1, MW || (de) := a
|-
| ld a,(de) || 00011010 || 2 || 7 (4,3) || M1, MR || a := (de)
|-
| ld (nn),a || 00110010 lolololo hihihihi || 4 || 13 (4,3,3,3) || M1, MR, MR, MW || (nn) := a
|-
| ld a,(nn) || 00111010 lolololo hihihihi || 4 || 13 (4,3,3,3) || M1, MR, MR, MR || a := (nn)
|-
| ld pp,nn || 00pp0001 lolololo hihihihi || 3 || 10 (4,3,3) || M1, MR, MR || rowspan=10|- || rowspan=10|- || rowspan=10|- || rowspan=10|- || rowspan=10|- || rowspan=10|- || rowspan=10|- || rowspan=10|- || pp := nn ||rowspan=10|16-bit Load
|-
| ld qq,nn || DD/FD 00qq0001 lolololo hihihihi || 4 || 14 (4,4,3,3) || M1, M1, MR, MR || qq := nn
|-
| ld (nn),hl || 00100010 lolololo hihihihi || 5 || 16 (4,3,3,3,3) || M1, MR, MR, MW, MW || (nn) := hl
|-
| ld (nn),ixy || DD/FD 00100010 lolololo hihihihi || 6 || 20 (4,4,3,3,3,3) || M1, M1, MR, MR, MW, MW || (nn) := ixy
|-
| ld (nn),pp || ED 01pp0011 lolololo hihihihi || 6 || 20 (4,4,3,3,3,3) || M1, M1, MR, MR, MW, MW || (nn) := pp
|-
| ld hl,(nn) || 00101010 lolololo hihihihi || 5 || 16 (4,3,3,3,3) || M1, MR, MR, MR, MR || hl := (nn)
|-
| ld ixy,(nn) || DD/FD 00101010 lolololo hihihihi || 6 || 20 (4,4,3,3,3,3) || M1, M1, MR, MR, MR, MR || ixy := (nn)
|-
| ld pp,(nn) || ED 01pp1011 lolololo hihihihi || 6 || 20 (4,4,3,3,3,3) || M1, M1, MR, MR, MR, MR || pp := (nn)
|-
| ld sp,hl || 11111001 || 2 || 6 (6) || M1, INT(2) || sp := hl
|-
| ld sp,ixy || DD/FD 11111001 || 3 || 10 (4,6) || M1, M1, INT(2) || sp := ixy
|-
| pop p̃p̃ || 11p̃p̃0001 || 3 || 10 (4,3,3) || M1, MR, MR || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || p̃p̃ := (sp), sp += 2 ||rowspan=2|Pop a value from the stack
|-
| pop q̃q̃ || DD/FD 11q̃q̃0001 || 4 || 14 (4,4,3,3) || M1, M1, MR, MR || q̃q̃ := (sp), sp += 2
|-
| push p̃p̃ || 11p̃p̃0101 || 4 || 11 (5,3,3) || M1, INT(1), MW, MW || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || rowspan=2|- || sp -= 2, (sp) := p̃p̃ ||rowspan=2|Push a value onto the stack
|-
| push q̃q̃ || DD/FD 11q̃q̃0101 11p̃p̃0101 || 5 || 15 (4,5,3,3) || M1, M1, INT(1), MW, MW || sp -= 2, (sp) := q̃q̃
|}
<sup>†</sup> Note: The cycle count `19` and breakdown `(4,4,3,2,3,3)` for `ld (ixy+d),n` is derived from standard Z80 timings (Prefix Fetch, Opcode Fetch, Read d, Read n, Internal Delay, Write n). Your original table implied `(4,4,3,5,3)` = 19T, which is less typical for this instruction; adjust if necessary based on your primary source.
This table now includes the M-Cycle sequence column, which should be directly usable for implementing the cycle-stepping logic in your Z80 emulator. Remember to handle the prefixes (`DD`/`FD`/`ED`/`CB`) correctly by fetching them first and then using the M-cycle sequence of the *underlying* instruction (often shifted, like `ld (ixy+d),r` being based on `ld (hl),r`).
=== 16-bit Arithmetic group ===
