Changes

SeeThe 6502 also has internal latches and buffers used for address handling and instruction execution. For example: [https*ABL/ABH:Address Bus Low//www.rightoHigh, latches for the address bus.com/2012/12*AI/BI: Input Registers for the-6502-overflow-flag-explainedALU.*IR: Instruction Register, holds the fetched instruction opcode byte while the CPU decodes and executes it.html The 6502 overflow flag explained mathematically]

Fun fact: the TMS9900 CPU took this further, and had by having no onboard registers (other than , except PC & status register). Everything was in RAM.

| ADC BIT || || || 69 (2) || 6D 2C (4) || 7D (4+p) || 79 (4+p) || || 65 24 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || Z || C - || A + ∧ M + CF , M₇ → ANF, CF M₆ → VF || ADd with Carrytest BITs

| ASL EOR || || 0A || 49 (2) || 4D (4) || 0E 5D (64+p) || 1E 59 (74+p) || || 45 (3) || 06 55 (54) || 16 || 41 (6) || 51 (5+p) || || N || - || - || - || Z || - || A ⊻ M → A || bitwise Exclusive OR|-| ORA || || || 09 (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || N || - || - || - || Z || - || A ∨ M → A || bitwise OR with Accumulator|-| ADC || || || 69 (2) || 6D (4) || 7D (4+p) || 79 (4+p) || || 65 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || Z || C || A + M + CF ← /→ A, CF || ADd with Carry|-| SBC || || || E9 (2) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (6) || F1 (5+p) || || N || V || - || - || Z || C || A - M₇...M₀/ ← 0 - (1 - CF) → A || Arithmetic Shift LeftSuBtract with Carry

| DEC ASL || || 0A (2) || || CE 0E (6) || DE 1E (7) || || || C6 06 (5) || D6 16 (6) || || || || || N || - || - || - || Z || - C || CF ← /M - 1 → ₇...M ₀/ ← 0 || DECrement memoryArithmetic Shift Left

| DEX LSR || CA || 4A (2) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || || N 0 || - || - || - || Z || - C || X - 1 0 → /M₇...M₀/ → X CF || DEcrement XLogical Shift Right

| DEY ROL || 88 || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || || 36 (6) || || || || || N || - || - || - || Z || - C || Y - 1 → Y CF ← /M₇...M₀/ ← CF || DEcrement YROtate Left

| EOR ROR || || 6A (2) || 49 || 6E (26) || 4D 7E (47) || 5D || || 66 (4+p5) || 59 76 (4+p6) || || 45 || || || N || - || - || - || Z || C || CF → /M₇...M₀/ → CF || ROtate Right|-| DEC || || || || CE (36) || 55 DE (47) || || 41 || C6 (65) || 51 D6 (5+p6) || || || || || N || - || - || - || Z || - || A ⊻ M - 1 → A M || bitwise Exclusive ORDECrement memory

| TYA PLP || 98 28 (24) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P || PuLl Processor status|-| PLA || 68 (4) || || || || || || || || || || || || N || - || - || - || Z || - || Y (S)↑ → A || Transfer Y to APuLl Accumulator|-| PHP || 08 (3) || || || || || || || || || || || || - || - || - || - || - || - || P↓ || PusH Processor status|-| PHA || 48 (3) || || || || || || || || || || || || - || - || - || - || - || - || A↓ || PusH Accumulator

! rowspan=2|Mnemonic !! colspan=12|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description

! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C 

| BCC JMP || || || 4C (3) || || || 6C (5) || || || || || || 90 (2+t+p) || - || - || - || - || - || - || - || Branch on CF = 0 [PC + 1] → PCL, [PC + 2] → PCH || Branch on Carry ClearJuMP

| BCS JSR || || || 20 (6) || || || || || || || || || B0 (2+t+p) || - || - || - || - || - || - || - || Branch on CF = PC + 2↓, [PC + 1 ] → PCL, [PC + 2] → PCH || Branch on Carry SetJump to SubRoutine

| BEQ RTS || 60 (6) || || || || || || || || || || || F0 (2+t+p) || - || - || - || - || - || - || - || Branch on ZF = (S)↑ → PCL, (S)↑ → PCH, PC + 1 → PC || Branch on EQualReTurn from Subroutine

| BIT RTI || 40 (6) || || 2C (4) || || || || 24 (3) || || || || || || N || V || - D || - || - I || Z || - C || A ∧ M(S)↑ → P, M₇ (S)↑ → NFPCL, M₆ (S)↑ → VF PCH || test BITsReTurn from Interrupt

| BMI BRK || 00 (7) || || || || || || || || || || || 30 (2+t+p) || - || - || - || - 1 || - || - || - || Branch on NF = 1 PC + 2↓, [FFFE] → PCL, [FFFF] → PCH || Branch on MInusBReaK

| BNE SEI || 78 (2) || || || || || || || || || || || D0 (2+t+p) || - || - || - || - || - 1 || - || - || Branch on ZF = 0 1 → IF || Branch on Not EqualSEt Interrupt flag

| BPL CLI || 58 (2) || || || || || || || || || || || 10 (2+t+p) || - || - || - || - || - 0 || - || - || Branch on NF = 0 → IF || Branch on PLusCLear Interrupt flag

| BRK SEC || 00 38 (72) || || || || || || || || || || || || - || - || 1 - || - || 1 || - || - 1 || PC + 2↓, [FFFE] → PCL, [FFFF] 1 → PCH CF || BReaKSEt Carry flag

| BVC CLC || 18 (2) || || || || || || || || || || || 50 (2+t+p) || - || - || - || - || - || - || - 0 || Branch on VF = 0 → CF || Branch on oVerflow ClearCLear Carry flag

| BVS SED || F8 (2) || || || || || || || || || || || 70 (2+t+p) || - || - || - || - 1 || - || - || - || Branch on VF = 1 → DF || Branch on oVerflow SetSEt Decimal flag

| CLC CLD || 18 D8 (2) || || || || || || || || || || || || - || - || - 0 || - || - || - || 0 || 0 → CF DF || CLear Carry Decimal flag

| CLD CLV || D8 B8 (2) || || || || || || || || || || || || - || - 0 || - || 0 || - || - || - || 0 → DF VF || CLear Decimal oVerflow flag

| CLI NOP || 58 EA (2) || || || || || || || || || || || || - || - || - || - || 0 || - || - || 0 → IF No operation || CLear Interrupt flagNo OPeration

| CLV BPL || B8 (2) || || || || || || || || || || || 10 (2+t+p) || - || 0 || - || - || - || - || - || Branch on NF = 0 → VF || CLear oVerflow flagBranch on PLus

| JMP BMI || || || 4C (3) || || || 6C (5) || || || || || || 30 (2+t+p) || - || - || - || - || - || - || - || [PC + Branch on NF = 1] → PCL, [PC + 2] → PCH || JuMPBranch on MInus

| JSR BVC || || || 20 (6) || || || || || || || || || 50 (2+t+p) || - || - || - || - || - || - || - || PC + 2↓, [PC + 1] → PCL, [PC + 2] → PCH Branch on VF = 0 || Jump to SubRoutineBranch on oVerflow Clear

| NOP BVS || EA (2) || || || || || || || || || || || 70 (2+t+p) || - || - || - || - || - || - || - || No operation Branch on VF = 1 || No OPerationBranch on oVerflow Set

| RTI BCC || 40 (6) || || || || || || || || || || || 90 (2+t+p) || N - || V - || - || D - || I - || Z - || C || (S)↑ → P, (S)↑ → PCL, (S)↑ → PCH Branch on CF = 0 || ReTurn from InterruptBranch on Carry Clear

| RTS BCS || 60 (6) || || || || || || || || || || || B0 (2+t+p) || - || - || - || - || - || - || - || (S)↑ → PCL, (S)↑ → PCH, PC + Branch on CF = 1 → PC || ReTurn from SubroutineBranch on Carry Set

| SEC BNE || 38 (2) || || || || || || || || || || || D0 (2+t+p) || - || - || - || - || - || - || 1 || 1 → CF Branch on ZF = 0 || SEt Carry flagBranch on Not Equal

| SED BEQ || F8 (2) || || || || || || || || || || || || - || - || - || 1 || - || - || - || 1 → DF || SEt Decimal flag|-| SEI || 78 F0 (2+t+p) || || || || || || || || || || || || - || - || - || - || 1 || - || - || Branch on ZF = 1 → IF || SEt Interrupt flagBranch on EQual

! rowspan=2|Mnemonic !! colspan=10|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description

! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! N !! V !! B !! D !! I !! Z !! C

| ALR DCP (ASRDCM) || || 4B || CF (26) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || || 0 || - N || - || - || - || Z || C || A AND oper, 0 M -> [76543210] 1 -> CF M, A - M || AND DEC oper + LSRCMP oper

| ANC ISC (ISB, INS) || || || 0B EF (26) || FF (7) || FB (7) || E7 (5) || F7 (6) || || E3 (8) || || F3 (8) || N || - || - V || - || - || Z || C || A AND oper, bit(7) M + 1 -> M, A - M - CF -> A || AND INC oper + set CF as ASLSBC oper

| ANC2 RLA || || 2B || 2F (26) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || 33 (8) || N || N - || - || - || Z || C || M = CF <- [76543210] <- CF, A AND M -> A || ROL oper + AND oper|-| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || Z || C || M = CF -> [76543210] -> CF, A AND + M + CF -> A, CF || ROR oper+ ADC oper|-| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- 0, bitA OR M -> A || ASL oper + ORA oper|-| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || Z || C || M = 0 -> [76543210] -> CF , A EOR M -> A || LSR oper + EOR oper|-| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper|-| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X|-| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper |-| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+ set CF as ROL1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work

| ANE (XAA) || || style="color: #CC0000;"|'''8B''' (2) || || || || || || || || || N || - || - || - || - || Z || - || (A OR magic) AND X AND oper -> A || * AND X + AND oper

| ARR LXA (LAX) ||| |style="color: #CC0000;"| 6B '''AB''' (2) || || || || || || || || || N || V || - || - || - || Z || C - || (A OR magic) AND oper, CF -> [76543210] A -> CF X || Store * AND oper + RORin A and Xhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Wizball on C64 requires a $EE magic constant for LXA

| DCP ALR (DCMASR) || || || CF 4B (62) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || N || - 0 || - || - || - || Z || C || M A AND oper, 0 - 1 > [76543210] -> M, A - M CF || DEC AND oper + CMP operLSR

| ISC ARR || || 6B (ISB, INS2) || || || EF (6) || FF || || || || || N || V || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR|-| ANC || || 0B (72) || FB || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || E7 AND oper + set CF as ASL|-| ANC2 || || 2B (52) || F7 || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(67) -> CF || AND oper + set CF as ROL|-| E3 SBX (8AXS, SAX) || F3 || CB (82) || N || V || || || || || || || N || - || - || - || Z || C || M + 1 (A AND X) - oper -> MX || CMP and DEX at once, sets flags like CMP|-| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || Z || C || A - M - ~CF -> A || INC SBC oper + SBC operNOP

|| || || || || || || || || || - || - || - || - || - || - || - || Stop execution || Halt the CPU. The processor will be trapped infinitely in T1 phase with $FF on the data bus. Reset required.|-| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper|-| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper|-| LXA (LAX) || || style="color: #CC0000;"|'''AB''' (2) || || || || || || || || || N || - || - || - || - || Z || - || (A OR magic) AND oper -> A -> X || Store * AND oper in A and Xhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Wizball on C64 requires a $EE magic constant for LXA

|| || || || - || - || - || - || - || - || - || No operation || No Operation|-| RLA || || || 2F (6) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || 33 (8) || N || - || - || - || - || Z || C || M = CF <- [76543210] <- CF, A AND M -> A || ROL oper + AND oper|-| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || - || Z || C || M = CF -> [76543210] -> CF, A + M + CF -> A, CF || ROR oper + ADC oper|-| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X|-| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP|-| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || - || Z || C || M = CF <- [76543210] <- 0, A OR M -> A || ASL oper + ORA oper|-| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || - || Z || C || M = 0 -> [76543210] -> CF, A EOR M -> A || LSR oper + EOR oper|-| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || - || Z || C || A - M - ~CF -> A || SBC oper + NOP

| 6C xx xx || JMP ''zpgind''

* The TXS instruction does not affect any flag, while all other transfer instructions do.* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.* The CLV (Clear Overflow Flag) instruction exist , but not the SEV (Set Overflow Flag) instruction.* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.

* The CMOS 65C02 fixed multiple bugs of the original NMOS 6502, but also removed access to all illegal instructions. Some cycle counts have been modified and some extra instructions have been added. In fact, there are multiple implementations of the 65C02 (WDC 65C02, WDC 65C02S, Rockwell R65C02, CSG 65CE02, ...), each with its own variant of the instruction set[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference].

* The WDC 65C816, used in the [[SNES]] and the [[Apple IIGS]], is a 16-bit version of the 65C02 [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet] [https://archive.org/details/SNESDevManual/ SNES development manual] [https://problemkaputt.de/fullsnes.htm Noca$h's fullsnes] [https://snes.nesdev.org/wiki/SNESdev_Wiki SNESdev wiki]. The 65C816 contains a compatibillity mode, enabled by default upon reset, that makes it behave like a regular 65C02. The full 65C816 cycle-by-cycle steps are in the [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet].