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! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! D !! I !! Z !! C
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| TAX || AA (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → X || Transfer A to X
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| TXA || 8A (2) || || || || || || || || || || || || N || - || - || - || Z || - || X → A || Transfer X to A
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| TAY || A8 (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → Y || Transfer A to Y
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| TYA || 98 (2) || || || || || || || || || || || || N || - || - || - || Z || - || Y → A || Transfer Y to A
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| TSX || BA (2) || || || || || || || || || || || || N || - || - || - || Z || - || S → X || Transfer Stack pointer to X
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| TXS || 9A (2) || || || || || || || || || || || || - || - || - || - || - || - || X → S || Transfer X to Stack pointer
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| LDA || || A9 (2) || AD (4) || BD (4+p) || B9 (4+p) || || A5 (3) || B5 (4) || || A1 (6) || B1 (5+p) || || N || - || - || - || Z || - || M → A || LoaD Accumulator
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| STY || || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || - || - || - || - || - || - || Y → M || STore Y register
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| TAX || AA (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → X || Transfer A to X
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| TXA || 8A (2) || || || || || || || || || || || || N || - || - || - || Z || - || X → A || Transfer X to A
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| TAY || A8 (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → Y || Transfer A to Y
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| TYA || 98 (2) || || || || || || || || || || || || N || - || - || - || Z || - || Y → A || Transfer Y to A
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| TSX || BA (2) || || || || || || || || || || || || N || - || - || - || Z || - || S → X || Transfer Stack pointer to X
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| TXS || 9A (2) || || || || || || || || || || || || - || - || - || - || - || - || X → S || Transfer X to Stack pointer
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| PLP || 28 (4) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P || PuLl Processor status
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| ARR || || 6B (2) || || || || || || || || || N || V || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR
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| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP
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| ANC || || 0B (2) || || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || AND oper + set CF as ASL
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| ANC2 || || 2B (2) || || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || AND oper + set CF as ROL
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| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP
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| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || Z || C || A - M - ~CF -> A || SBC oper + NOP
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The TXS instruction does not affect any flag, while all other transfer instructions do.
* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.* The CLV (Clear Overflow Flag) instruction exist , but not the SEV (Set Overflow Flag) instruction.
* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.