The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).
Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms).
*Detecting corruption in the PSG registers when a register write is not validated. [https://www.cpcwiki.eu/forum/programming/interesting-walkthrough-video-coding-a-pet-to-play-samples-at-60khz/msg250874/#msg250874 Source]
*Playing with the "floating" bus. Using Z80 read I/O commands to write to chip registers. Accessing ghost registers. Using undocumented I/O ports. Writing to multiple chips simultaneously. Changing PPI and PSG ports direction.
*Focusing on the minute details in [[Z80]], [[CRTC]], [[8255|PPI]] and [[PAL16L8|PAL]] chips. They are most often wrong in emulators.