Changes
Undo revision 126273 by [[Special:Contributions/Longshot|Longshot]] ([[User talk:Longshot|talk]]) Repairing the wiki
Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]
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== Interrupt generation ==
* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné ([[Longshot]])''
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC
When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.
Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.
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== CSYNC signal ==
* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné ([[Longshot]])''
The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.
When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.
If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.
C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).
For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.
On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.
The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.
If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.
The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.
C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.
On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.
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