Changes
Interruption chapter
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== Interrupt generation ==
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
The CPU maskable interrupts are generated by the Gate Array.
This is done by using a 6bits internal counter and monitoring the HSync and VSync signals produced by the CRTC.
On every falling edge of the HSync signal, the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate.
When the CPU acknowledge the interrupt (eg. it is going to jump to the interrupt vector), the Gate Array will reset bit5 of the counter, so the next interrupt can't occur closer than 32 HSync.
When a VSync occurs, the Gate Array will wait for two HSync and:
* If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.
* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.
This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed.
So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.
The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…
Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.
=== Timings ===
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC).
=== DI in peace ===
[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]
The GA maintains its int request until it is accepted.
RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.
But after the EI, a test similar to the one seen for the VBL is performed:
The interrupt is generated anyway, but:
* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).
* Otherwise, IC = 0.
== Controlling the Gate Array ==
