== Effort done ==
'''Instruction timing''' : I tested instruction timing of T80 compare to instruction timing of JavaCPC emulator, . I deduce also the memory access that had synchronization of Z80 with CRTC on M1 signal by WAIT_n insertion in order to be slow down a multiple of 4 Tstates per instruction. I deduce also one WAIT_n inserted during MEM_WR operation.
'''Test of a real Zilog 80''', in fact the only difference between T80 of opencore and real Z80 is that T80 run on rising_edge, and zilog Z80 run during low state, so for testing I had to indirectly . Test past with little modification of sequencer forcing it do nothing during low state of z80, resulting a downclock, it runclockdown (memory are too overclocked with this sequencer modification), perhaps if I put using buffer on zilog access I address bus and data bus could clock it at normal speed, solve this detail... but as it run..runs for me it is not a problem.
'''Alignment of HSYNC Interrupt''' : a button of starter kit display HSYNC interrupt loopback lines, it's usefull to compare to a Maxam test that alternate color on them
'''Sniffing of a real Amstrad''', I listen to some wires of my Amstrad CPC 6128 plus, but I can't access VSYNC/HSYNC output of CRTC, so I have to buy another model in order to do this test. In fact you can listen at clock of Amstrad and transmit it to FPGA DCM component, resulting a accelerated clock sequence, that's it, with FPGA DCM you can overclock output Amstrad clock signal in order to insert more operations, I use this tip for listening signals and save them inside starter kit asynchronous RAM (write, stop write, write, stop write... i'm a perfectionist paranoid...)