Real Amstrad use buffer memory in front of each address and data access, and real z80 is clock low state active. Normally if you follow datasheet of z80 you know how to map memory following CU comportment. Or you do as Amstrad, saying that z80 CU sucks, I create my own sequencer, managing all my memories access, alternating CRTC work and z80 work with little synchronization, insert by the way more pixels that can support my small CRTC...
How to use a sequence in VHDL :
if rising_edge(master_clk) then
if seq="00" then
elsif seq="01" then
elsif seq="10" then
else
end if
end if
What not to do :
if rising_edge(seq[0]) then
end if
Because that can auto-generate bad unwanted sub-clocks...
If you know more than me about sequencing clocks with Xilinx's DCM and Altera's PPL (making a true clock sequence without auto-generate unwanted sub-clock), do post on [http://mamevhdl.wordpress.com/2013/09/21/clocks-device/ MameVHDL : CLOCKS device].
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