Changes
CRTC
,/* CUDISP */
CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.
However, this signal is present on provided to the expansion port. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
== DISPTMG ==
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only Only
|}
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
'''Notes'''
* On type 0 The CRTC is not connected to the CPU's RD and 1WR pins, so the CRTC is not aware of the CPU bus I/O direction. Therefore, if a Write Only register is read frominstruction is used on a write register of the CRTC, "0" then a data is returnedsent to the CRTC.
* CRTC type 4 On types 0 and 1, if a Write Only register is the same as read from, "0" is returned. * CRTC type types 3. The registers also repeat as they do on and 4 are identical in every way, except for the type 3unlocking mechanism specific to the ASIC.
* See the document "Extra CPC Plus Hardware Information" for more details.
=== Horizontal and Vertical Sync (R3) ===
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 1..0 define the interlace mode (00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video).
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.
