Changes
/* PAL MMR register */
[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum
== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the Gate Array can only access the Base 64k page of RAM.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|colspan=2|'''MMR'''||colspan=3|'''64K page'''||'''S'''||colspan=2|'''MM'''||colspan=4 style="text-align: center;"|'''CPU Memory Mapping'''
|-
|'''7'''
|'''6'''
|'''5'''
|'''4'''
|'''3'''
|'''2'''
|'''1'''
|'''0'''
|style="text-align: center;"|'''&0000-&3fff'''
|style="text-align: center;"|'''&4000-&7fff'''
|style="text-align: center;"|'''&8000-&bfff'''
|style="text-align: center;"|'''&c000-&ffff'''
|-
|1
|1
|colspan=3 style="text-align: center;"|x
|0
|0
|0
|Base 64k / Bank 0
|Base 64k / Bank 1
|Base 64k / Bank 2
|Base 64k / Bank 3
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|0
|0
|1
|Base 64k / Bank 0
|Base 64k / Bank 1
|Base 64k / Bank 2
|'''Page p / Bank 3'''
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|0
|1
|0
|'''Page p / Bank 0'''
|'''Page p / Bank 1'''
|'''Page p / Bank 2'''
|'''Page p / Bank 3'''
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|0
|1
|1
|Base 64k / Bank 0
|'''Base 64k / Bank 3'''
|Base 64k / Bank 2
|'''Page p / Bank 3'''
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|1
|colspan=2 style="text-align: center;"|b
|Base 64k / Bank 0
|'''Page p / Bank b'''
|Base 64k / Bank 2
|Base 64k / Bank 3
|}
== PAL I/O port ==
Bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1, 2. It can be at 0 or 1 on CRTCs 3 and 4.
== See also ==
*CPC 464/664 cannot deal with A14/A15 for bank 0 Base 64k page like the 6128 does. So external RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]
*[[Gate Array and ASIC Pin-Outs]]
*[[Standard Memory Expansions]]
[[Category:Datasheet]]
