The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.
== Interrupt management ==
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter (R52) that counts from 0 to 51, incrementing after each HSYNC signal.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC
When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''', bit5 of R52 is cleared and the interrupt takes place
== Controlling the Gate Array ==
|2 pixels in 4 colors
|}
== Split rasters ==
On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.
On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.
To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll register (SSR) to finely adjust the horizontal position of the graphics.
== Palette R,G,B definitions ==
There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.
To display a CPC image you will need to use a analogue monitor with a composite sync.
=== Palette sorted by Hardware Colour Numbers ===