Changes
CRTC
,/* The 6845 Registers */ Add explanation
The '''CRTC''' (Cathode Ray Tube Controller) generates helps to generate the video signal of the Amstrad CPC.
== Overview ==
The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.
1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.
2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.
3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.
* In most cases, the type of the detected 6845 is reported.
4. As far as I know, the KC compact used HD6845S HD6845R only.
== Timings and relating with Z80 instructions count ==
|''Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA12 MA13
|-
|A14||6845||MA11 MA12
|-
|A13||6845||RA2
== DISPTMG ==
DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2 or 5. The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
== HSYNC and VSYNC ==
On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array. The When HSYNC is active Gate-Array modifies outputs the signals and palette colour black. If the HSYNC is set to 14 characters then mixes these black will be output for 14us. The HSYNC is modified before being sent to form the Composite-Sync which monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51. On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array. The VSYNC is also modified before being sent to the display monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.
Using CRTC1, VSYNC width value 0 means a value of 16.
== The 6845 Registers ==
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||3248
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memoryfor hardware scrolling, useful when and if using memory from address &0000with the firmware.
|-
|14||Cursor Address (High)||xx000000||0
|-
|15||Cursor Address (HighLow)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only
|-
|17||Light Pen Address (HighLow)||00000000||||Read Only
|-
|}
registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.
Details about Reg. 12 and Reg. 13 specifically:
'--'--'--------------' '--'--'---------------'
So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
== CRTC Differences ==
|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (HighLow)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}
3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.
== Horizontal and Vertical Sync (R3) ==
UM6845:
Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
UM6845R:
Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
MC6845:
Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
Pre-ASIC/ASIC:
Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
== UM6845R and R31 ==
R31 is described in the UM6845R documentation as "Dummy Register".
Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.
In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.
R31 doesn't exist on types 0,2,3.
== UM6845R and R12/R13 ==
The UM6845R differs to other CRTC in respect of R12/R13.
When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.
Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.
In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.
== UM6845R status register ==
The UM6845R has a status register that can be read using port &BExx.
Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.
Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.
It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.
All the other bits read as 0 and don't have any function.
== Datasheets ==
* [[Media:hd6845.hitachi.pdf|HD6845 HD6845S (Hitachi) (aka type 0)]]
* [[Media:Um6845.umc.pdf|UM6845 (UMC) (aka type 0)]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
