LD BC,&FF64
LD A,14
OUT (C),CA
LD BC,&FF63
LD A,0
LD BC,&FF64
LD A,14
OUT (C),CA
LD BC,&FF63
LD A,3
LD BC,&FF64
LD A,14
OUT (C),CA
LD BC,&FF63
LD A,3
LD BC,&FF64
LD A,14
OUT (C),CA
LD BC,&FF63
LD A,2
So you need to know when each mask register is used and you need to understand the logical->physical VRAM mapping.
===== Write Mask in P1 mode =====
* Document states "In P1 mode, writing is prohibited on the side not specified as the transfer destination. (Layer "A":R#46, Layer "B":R#47)". I haven't discovered what this actually means yet.
===== Write Mask in bitmap and standby modes =====
[[Category:HardwareElectronic Component]]