Changes

The CPC6128 second bank of 64K RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.

On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished. == Fixed version (Gerald) ==Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.   A14OUT = !( !A14 # !A15 & !Q0 & Q2 ); A15OUT = !( !A15 & !A14 # !A15 & !Q1 # !A15 & !Q0 & !Q2 ); Q0 = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR # !D7ANDD6 & nRESET & Q0 # nRESET & A15 & Q0 # nRESET & nIOWR & Q0 ); Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR # !D7ANDD6 & nRESET & Q1 # nRESET & A15 & Q1 # nRESET & nIOWR & Q1 ); Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR # !D7ANDD6 & nRESET & Q2 # nRESET & A15 & Q2 # nRESET & nIOWR & Q2 ); nCAS0 = ( nCAS # RAMDIS & !nCPU & nCAS0 # !A15 & A14 & !nCPU & Q2 & nCAS0 # A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0 # !nCPU & !Q0 & Q1 & !Q2 & nCAS0 # !nCAS1 ); nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0 # !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0 # !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0 # !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1 # !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1 # !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 ); [[File:CPC6128.JED]] : Fixed version of Amstrad 40031 GAL replacement [[File:CPC6128.hex]] : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version. == Initial replacement equation (Porchy) == The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

[[File:Amstrad6128.jed ]] Original JED File posted on CPCWiki Forum == See also == *For RAM banking settings see Register 3 of the [[Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address). *[[Gate Array and ASIC Pin-Outs]] [[Category:Datasheet]]