Changes

Jump to: navigation, search

Gate Array and ASIC Pin-Outs

268 bytes added, 13:25, 18 March 2022
Added links to gate array and PAL pages
[[Category:Electronic Component]]== 40pin Gate Array 40007 (20RA043) ==
Old CPC464 version (with cooling plate).
1 /CPU ADDR
VCC1=+5V (direct), VCC2=+5V (via resistor)
== 40pin Gate Array 40008 or ==An updated, pin compatible version of the 40007. The 40008 like the 40007 required a heatsink. == 40pin Gate Array 40010 (HSG3130 or HSG3170) ==Newer versions version of Gate Array, with a rearranged pin-outs (other than 40007)out. The 40010 and 40008 have same pin-outs. 40010 has no didn't required a cooling plate. 40008 seems to be rare (no info if it has cooling plate or not). 
1 D5
2 D6
5 D1
6 D2
7 /CASNCAS
8 A15
9 A14
11 /CPU
12 A15OUT
13 NC* 14 NC* 15 NC*
16 /CAS1
17 /CAS0
18 /IOWR
19 A14OUT
20 UNDOC (VCC?)
When PAL not installed: Close LK5,LK6,LK8 for 64K version.
(* NC but signals exist on those pins)
== 100pin Gate Array AMS40226 (ARN4) ==
Pre-ASIC (late cost-down models).
See CPC6128 "ULA/DS" section in service manualAmendment Service Manual.
Aside from Gate Array, it includes CRTC, probably PAL, FDC select/motor, DRAM
addr/data bus, RESET signals.
1 SCLKI
2 UNDOC1VCC 3 UNDOC2GND
4 /ROM1 (BIOS,BAS)
5 /ROM2 (AMSDOS)
12 RA1
13 RA0
14 UNDOC1VCC 15 UNDOC2GND
16 /CAS0
17 /CAS1
33 PLLCK (CLK8, too?)
34 RDTA
35 UNDOC3 ?DATA (undocumented optional output to FDC) 36 UNDOC4 ?WINDOW (undocumented optional output to FDC)
37 RED
38 GRE
39 BLU
40 UNDOC2GND 41 UNDOC1VCC
42 /SYNC
43 CLK4
50 /ROMEN
51 /RESET
52 UNDOC2GND 53 UNDOC1VCC
54 /BRST (BUS RESET)
55 READY
64 D2
65 D3
66 UNDOC2GND 67 UNDOC1VCC
68 D4
69 D5
87 A15
88 /IOW
89 UNDOC2GND 90 UNDOC1VCC
91 /IOR
92 /PSTB (Printer Select) (Ann OR /IOW) (this is not STROBE)
Printer port 74LS273 chip is replaced by TWO chips: 74LS174 and 74LS175 (the
latter one includes strobe inversion).
UNDOC1Pin 35/UNDOC2 36 are probably VCC/GNDnot documented on schematic, but from PCB layout they can be connected to FDC by links. UNDOC3/UNDOC4 These are unknownoutput of internal FDC data separator.
== 160pin ASIC (CPC+/GX4000) ==
15 A6
16 VCC
 
== See also ==
 
*[[Gate Array]]
 
*[[PAL16L8]]
7
edits