Changes
/* Sniffing USB frames */ typo
[[File:ghostngoblins.jpg]]
== How to assemble it ==NEXYS2 Xilinx version is obsolete, it is still describe here for history reason (showing the prototyping part). Please refer to [[http://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad MiST-board CoreDocAmstrad]] for the final user version, running on MiST-board platform.
'''You need:'''
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==Video==
http://www.youtube.com/watch?v=Z8FB_eIy8LY
== Last news about this project ==
In MaY 2020, I add Sorgelig formula for WAIT_n=quick, no more table of instruction time in code, just a simple WAIT_n formula. In MaY 2019, I add cassette feature. In August 2018, totally desperated -around time and level of efforts- about reaching next step focus around Z80 range, here came Sorgelig, he is working around port of FPGAmstrad into the MiSTer FPGA platform, and make during his step an intermediate jump step on MiST-board called "Amstrad_MiST" full of verilog as he seems to love. And, as a specialist of Z80 core, I just send him Z80 testbenches I collected since, he then corrected the Z80 fully this way, I merged, resulting this next current checkpoint. In May 2018, I programmed my first CPC game http://www.pouet.net/prod.php?which=75855 following JDVA youtube tutorial since january, they are based on CPCMania 2005's website knowledge about programing in CPC using SDCC. I think that if I do progress this way enough, I'll implement my own CPC testbenches, needed for reaching next realise of FPGAmstrad (I did it : Moustache testbench) [[File:Mk2-cpc-600x350.png|thumbnail|Image converted to CPC by SuTeKH/Epyteo]] In January 2018, Jepalza has ported FPGAmstrad from this wiki (Xilinx version, principe of concept 2011) on spanish ZX-Uno low-cost FPGA final platform (three times cheaper than MiST-board/same Xilinx chip poc 2011/chip used at 100%). So I bought a ZX-Uno to help around this fork, merging components. Normaly I can go a little further later (CRTC0, joystick), and then go back to MiST-board :) https://www.youtube.com/watch?v=tpr9xxx1rsA In May 2017, FPGAmstrad TV mode is validated using a TV from Tetalab group. In February 2017, CRTC1 is also implemented following JavaCPC's source code, now you can choose between CRTC0 and CRTC1 in the OSD menu. In January 2017, scanlines mode is implemented, you can select it from the OSD menu. In December 2017, implementing green screen, using "Les Sucres en Morceaux" tutorial. In September 2016, FPGAmstrad does use external RAM as RAM+VRAM, no more "LowerVRAM/UpperVRAM" switches to select in the OSD menu.
[[File:Fpgamstrad jocker batdemo.png|thumbnail|Using 64K of VRAM...]]
In November 2014, I bought MiST-board, with two USB pro joysticks.
In September 2014, I bought NEXYS4, more powerfull than NEXYS2, with same external RAM, internal mini-sd, no PS/2 (it is a pmod option)... I have some patchs to make (MSB FAT32 offset). I would like to make a USB snifer sniffer also with it (usb to ethernet (wireshark))
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===On MiST-board CoreAmstrad version===
Games that doesn't run are :
*'''007 The Living Daylight.dsk''': problem with VSYNC. Certainly two VSYNC per frame, GA ignoring the second one.
*'''ACPC_logon_system.dsk''': text scrolling lag. This demo will be used for horizontal ink calibration (when I’ll buy a luxurious FPGA platform... I need in fact 224KB of internal RAM to do it), and CRTC overcounts.
*'''split ink demo.dsk''': (from cpcrulez) : may help about ink raster calibration.
*'''Sultan's Maze.dsk''': does need the right part of keyboard (F0-F9 are used for directions in this game)
*'''Orion Primes.dsk''': does display "secteurs entrelacés" - "vérifiez votre copie", a FDC problem, perhaps "sectorId++" is not the good way to reach next sector, or else two tracks in one track. Does pass on Sorgelig fork.*'''Batman_Forever.dsk''': some problem during flying chip demo part(one garbage line), and several rupture showing ghost lines around Vcc=0.Rupture solved in r005.8.16c4, but flying chip now show a half garbage of pixels. Batman seems CRTC1. Problems with FDC in r005.8.16 (does slow animations, like if I missed some "not ready" signal ?)*'''30YMD.dsk''': in Benediction demo, at bottom some time you see some ghosts of central animation (too many HSync per screen ?)*'''arkanoid2.dsk''': don't run in r005.8.13, but fine solved in r005.8.13e 16 (experimental forkCRTC0 seems perfectly implemented), ok in r005.8.14 (using default OSD value : MEM_WR=quick)*'''trailblazer.dsk''': no more "raster" problem since r005.530YMD seems CRTC0, it's now perfect ! Palette heuristic offset running fine except that changing disk feature does still fail (done for unlocking Batman Forever Demo) has a small effect in left (squares are inserted/not separated by a black line in first column) - same small defect in TV mode using r005.8.14.2... Thinking about a HSYNC offset of 2 (instead of 1 currently) then also delaying DATA+HDISP of 1 (charinserted/inserted signal ?)*'''imperial_mahjong.dsk''': modern EXA/EXA2 resolution not passing my color pallet heuristic :p- does pass on Sorgelig fork.
*'''rtypeee.dsk''': at begin of presentation, a draw of "jack plug" is done in a strange video mode, more than 200 pixels of height !, see [http://cpc.sylvestre.org/musee/musee_flipping_lace.html flipping lace]
*'''S&Koh.dsk''': LOGON SYSTEM, black screen in r005.8.4... damn
*'''Pinball_Dreams__PREVIEWFres Fighter II Turbo.DSKdsk''': Does run FDC problem, cannot be launched.*'''Seascape.dsk''': Devilmarkus, using scandb50Hz and MEM_wr=slow, does display, but a flower petal at bottom is drawn in experimentalblue. A good raster test. Test on real 6128 [http:/ versions /www.cpcwiki.eu/forum/demos/seascape-cpc-by-impact-on-original-cpc-6128/ forum: Seascape CPC by Impact - on original CPC 6128 ?] - by Emashzed : type 1 is perfect (no blue on bottom right flowers, no blue on middle triangle rock), type 2 has bright cyan squares (one on bottom right flowers, and one on middle triangle rock. Calibrated OK in r005.8.916.2 and 5 using OSD VGA:scandb50Hz. Does pass on Sorgelig fork.[[File:Seaspace-type1_MiST-board_CoreAmstrad-r005.98.16.11e 5|thumbnail|Seascape (experimental forked version of type 1) - r005.98.11 using flag FPGAmstrad_amstrad_motherboard16.vhdl5]]*'''Megablasters[original].HACK_Z80=false)dsk''': has a 2 pixels glich border on left side. Does freeze Certainly final HSYNC offset problem, as on Super Cauldron normaly the right (not left) border has to be selected to get a nice bottom bar in !experimental versions when background music is special game (actually too centered)*'''Edge_Grinder.dsk''': screen not long classic background stable horizontally, music) and you press two buttons change speed during game ? Does pass on Sorgelig fork.*'''Welcome To Amstrad CPC 6128.dsk''': does display "Incompatible BASIC installed" message.*'''phX.dsk''': does begin to pass on r005.8.16. Does pass completly on Sorgelig fork (left/right flipper keysscandoubler) . Does finish on amstrad_180804_r005.8.16.5. Does show vertical bars with CRTC0, no display during end scroll part. Does freeze at middle on amstrad_180804_r005.8.16.6 (doesn't launch the same read of disk), does pass on Sorgelig fork but song is 2 times slown down before reaching this part. Did pass one timeon amstrad_200527_r005.8.16.8.5c1.rbf (CRTC0 WAIT_n:quick (Sorgelig GA simple formula)), ok but I was lucky. Did pass one time on amstrad_200527_r005.8.16.8.5c2.rbf (CRTC1 WAIT_n:quick) except vertical bars of begin. Seems that launching Pinball Dreams CRTC1 (until menu of boards) before (soft reset (page up key) and) PhX CRTC0 does unlock PhX.*'''Ghouls'n'Ghost.dsk''': does fail on r005.8.16.2 : time going to zero in 3 seconds, is fine in r005.8.14 15.2, fine also on Sorgelig fork... also unlocked by Sorgelig in r005.8.16.3 !* '''Ultimate Megademo (using default OSD value Face Hugger).dsk''': MEM_WR=quickFirst part is better using CRTC0. Ending part (one just after Lemmings part), a double VSYNC problem (a small scrolling text instead of... a lot of things), music OK during this ending.
'''Arkanoid.dsk''' stars use rupture address (changing address several time during display of one image), it is now supported on "candidate 001" version of FPGAmstrad. Run better in r005.9.11e than in r005.9.11.
'''Ghouls'n'Ghost.dsk''' / '''Ecole.dsk''' does need RAM write when writing in ROM (RAM is beside ROM, hard to emulate with asynchronous SDRAM controler, MiST does use a hacked synchronous RAM done for that)
'''moktar.dsk''' / '''super_cauldron.dsk''' does run fine since r004.8.1.1. Morkar run fine in r005.8.16c4 using CRTC0 and MEM_wr=slow. Super Cauldron bottom bar is fine in r005.8.16.4 when we select "right border" (instead of default left one) during "screen synchro" menu welcome.
'''CPC Aventure''' does run fine since r005.2 (message about turning disk now displayed)
'''-circles.dsk''': this demo freeze does since r004.8 (PPI border effect ?) and is back since r005.5, it was nice to calibrate SOUND clock : I did generate 8 candidates of synchronizing this clock (1MHz from 4MHz : 1100 0110 0011 1001, and 0.5 deltas : 1100i, 0110i, 0011i, 1001i), only one does not freeze -circles... so I release r005.5 candidate. This demo is a great one around calibrating Yamaha clock.
'''Nigel Mansell's Grand Prix.dsk''': Only one race track seems ok : Monaco (Brazil track does not start). Unclassified : this disk bug also with other emulators, certainly a bad dsk dump here, TOSEC version of Nigel Mansell does run fine (but some legendary traces of "SK bit purpose" needed by here (in FDC, setting SK does jump deleted disk tracks), perhaps to investigate)- update : some tracks unlocked in r005.8.15c61.
'''saboteur2.dsk''': run fine since r005.5 (nice music and then freeze problem), it was about Yamaha clock generator (generated by Gatearray, versus WAIT_n added in short Z80 instruction to let them during all 4 clocks (Z80 in Amstrad does use 4T or 8T instructions (WAIT_n does insert missing T)). Does freeze at welcome since r005.8.7. Back since r005.8.10.
'''tetris95.dsk''' : bad in r005.8.9.2 (4 beep while breaking 3 lines (instead of 3 beep while breaking 3 lines), was correct in r005.8.4. Back since r005.8.10.
'''Battro.dsk''' seems also CRTC1 and does fail completly. Does pass in r005.8.16.
'''arkanoid2.dsk''': don't run in r005.8.13, but fine in r005.8.13e (experimental fork), ok in r005.8.14 (using default OSD value : MEM_WR=quick)
'''trailblazer.dsk''': no more "raster" problem since r005.5, it's now perfect ! Palette heuristic offset (done for unlocking Batman Forever Demo) has a small effect in left (squares are not separated by a black line in first column) - same small defect in TV mode using r005.8.14.2... Thinking about a HSYNC offset of 2 (instead of 1 currently) then also delaying DATA+HDISP of 1 (char) . Has defect on bottom scroll text bar r005.8.16.2, is fine in r005.8.15.2, fine also on Sorgelig fork... also unlocked by Sorgelig in r005.8.16.3 !
'''commando.dsk''': pixels that should be deleted are not deleted (only VRAM &C000-FFFF seems used), on level 1, the moto is not displayed correctly inside the bridge... but after the bridge :/ - unlocked by Sorgelig in r005.8.16.3 !
'''Pinball_Dreams__PREVIEW.DSK''': Does run in version r005.8.16.6 using CRTC1 (and WAIT_n=slow). Sorgelig fork does implement interlace (used an welcome screen - eagle)
{| class="wikitable"
*To test also : [http://www.speccy.pl/archive/prod.php?id=335 Unlimited Bobs (Dr.Piotr).dsk] demo.
== Effort done =On MiST-board CoreAmstrad version - TAPES ===
In r005fact CRTC1 is the best one.8CRTC2 is the low cost version. CRTC0 did appears before CRTC1.4, arnoldemu testbench "cpctest" does fail :/
In r005.8.15. WakeUp! (CRTC0/MEM_wr quick) detected as Emu first time, and after a quick reset, does say detected as CRTC0. In ZX-Uno FPGAmstrad, I implemented CRTC0. CRTC1 has double sized VSYNC against CRTC0 (moustache test) ===== TODO VGA: arnoldemu testbench - crtctest =VRAM ====Adding choice of CRTC 0 or 1 on OSD, and passing this test could be greatram_palette.
VRAM contains 800x300 amstrad pixels (VZoom x2), displayed VGA 800x600@72Hz with fix regular border at 768×576 and fix inside border at 768×544.
In ZX-Uno, VRAM contains 800x300 amstrad pixels (VZoom x2), displayed 640x480@60Hz, with vertical only border.
* simple_GateArrayInterrupt.vhd (GA to VRAM) parameters : VRAM_Hoffset/VRAM_Voffset
To calibrate : VRAM_Hoffset++ does offset one char left. VRAM_Voffset++ does offset one line up. On display H_BEGIN does begin to scan lines of VRAM. But V_BEGIN does not enter in consideration here : vertical=0 does begin to scan columns of VRAM.
In original CPC, top border has 1/2 char more than bottom border. I used Batman Forever default welcome/calibration screen to calibrate VRAM offsets. On ZX-Uno I used Arkanoid to calibrate VRAM offsets.
RAM_palette contains the ink list and the mode for each line of VRAM, sampled at horizontal middle of 800x600 screen, and used at begin of each line.
=== = VGA: TODO : arnoldemu testbench ===='''arnoldemu testbench: crtctest''' Adding choice of CRTC 0 or 1 on OSD, and passing this test could be great. ==== VGA: TODO : winape testbench ===='''winape testbench: plustest''' a better border heuristic Using winape testbench (plustest), test 2 does show somes problems while border does go out of screen, negative border does hide line itself. === bootloader ===SDCARD and RAM. (nothing to say here, really ???) === GA === ==== GA: alignment of HSYNC Interrupt ====Interrupt are respected since version "candidate 001" of FPGAmstrad, Markus does help me a lot about it. [[File:JavaCPC_running_norecess.jpg]] JavaCPC running norecess's "using-interrupts" code [[http://norecess.cpcscene.net/using-interrupts.html]] It could be interesting to test this asm code on next version of FPGAmstrad. ==== GA: Sniffing of a real Amstrad ====
[[File: cpc_plus_m1.jpg]]
Code name: Raptor
You can power Amstrad CPC using extension port, applying 5v. By doing it, power down button of Amstrad doesn’t run. Using this way you reach a common 5v power between starter-kit and Amstrad. I connected wires from extension port directly to FPGA, as they are used just for listening.
=== ROM and RAM extension =GA: WAIT_n generator - currently in r008.5.14 ====Instruction timing.
An elegant fork by Sorgelig, sum up nicely the "MEM_WR:slow" algorithm + the HACK_Z80 flag of r008.5.14 : T80pa CPU ( (...) .cen_p(ce_4p & (WAIT_n | no_wait)), .wait_n(1) // (cyc1MHz | (IORQ_n & MREQ_n) | no_wait) ); // Current WAIT_n generation is not correct! // It should use WAIT_n instead (see commented out code above ^^) reg WAIT_n; wire acc =(MREQ_n | ~RFSH_n) & IORQ_n; always @(posedge clk) begin reg old_acc; if(ce_4p) begin old_acc <=acc; if(old_acc & ~acc) WAIT_n <=0; if(cyc1MHz) WAIT_n <= PWM ====1; end end
If interruption r52 is regular, even while making a continues MEM_WR, interruption (int<==== Stereo sound output ====[[File:STarKos1 21 FPGAmstrad_800x600.png|none|STarKos '1.21 running on FPGAmstrad]]') shall be taken into account above WAIT_n insertions ?
==== TODO GA: SNAP DSK WAIT_n generator - talk about r005.8.16 ====Add an option in OSD MENU menu has now "WAIT_n: slow|quick"SNAP DSK". Does create , a copy of current disk in current drive into "SNAP[number]WAIT_n generator is implemented adding 0, 1 or 2 WAIT_n per instruction.DSK". Heuristic for number : file count (at boot, incremented at each snap dsk done)
In r005.8..too slow to execute a READ_DATA in Basic.7, arnoldemu testbench "cpctest" is OK
In r005.8..too slow to execute 16c29, arnoldemu testbench "cpctest" is OK (but it is a READ_DATA in Basic.wip version :p)
==== perl FDC frame decoder GA: Moustache testbench ====Adding a snifer A homemade Testbench done firstly for helping Sorgelig to calibrate it's port of FPGAmstrad into UPD765AMiSTer.java But as Sorgelig core does run finer than mine (Pinball Dreams did pass ! WAIT_n: writePort(int portslow, int value){System.out.println("writePort "+Util.hex((byte)port)+" "+Util.hex((byte)value)); readPort(int port) { System.out.println("writePort "+Util.hex((byte)port)+" "+Util.hex((byte)status)); return status; // just before this System.out.println("writePort "+Util.hex((byte)port)+" "+Util.hex((byte)data)); return data; // just before thatfdcMessages.pl # perl fdcMessages.pl < test.dsk.snifer.txt > test.snif.txt # perl fdcMessages.pl < orion.dsk.snifer.txt > orion.snif.txt use Switch; my $param_count=0;my $data_read_count=0;my $data_write_count=0;my $result_count=0; while(my $var = <>){ # print $var."\n"; if ($var =~ /^writePort ([0-9A-F][0-9A-F]) ([0-9A-F][0-9A-F])$/) { my $addr=$CRTC 1;my $value=hex($2); $value_hex=sprintf ("%02X", $value );$value_bin=sprintf ("%08b", $value ); if ($param_count>0) { $param_count--; if ($param_count eq 4 or $param_count eq 2) { print "W$param_count $value_bin $value_hex\n"; } else { print "W$param_count $value_bin\n"; } } elsif ($data_write_count>0) { $data_write_count--; #print "W $value_hex $data_write_count\n"; if ($data_write_count eq 511) { print "W $value_hex "; } elsif ($data_write_count>0) { print "$value_hex "; } else { print "$value_hex\n"; } } else { $result_count=0;$data_read_count=0; print "COMMAND "; switch($value_bin) { case /00110$/ { print "READ_DATA $value_bin\n"; $param_count=8;$data_read_count=512;$result_count=7;} case /01100$/ { print "READ_DELETED_DATA $value_bin\n"; $param_count=8;$data_read_count=512;$result_count=7;} case /00101$/ { print "WRITE_DATA $value_bin\n"; $param_count=8;$data_write_count=512;$result_count=7;} case /01001$/ { print "WRITE_DELETED_DATA $value_bin\n"; $param_count=8;$data_write_count=512;$result_count=7;} case /00010$/ { print "READ_DIAGNOSTIC $value_bin\n"; $param_count=8;$data_read_count=512;$result_count=7;} case /01010$/ { print "READ_ID $value_bin\n"; $param_count=1;$result_count=7;} case /01101$/ { print "WRITE_ID $value_bin (Format Write)\n"; $param_count=5;$result_count=7;} case /10001$/ { print "SCAN_EQUAL $value_bin\n"; $param_count=8;$data_read_count=512;$result_count=7;} case /11001$/ { print "SCAN_LOW_OR_EQUAL $value_bin\n"; $param_count=8;$data_read_count=512;$result_count=7;} case /11101$/ { print "SCAN_HIGH_OR_EQUAL $value_bin\n"; $param_count=8;$data_read_count=512;$result_count=7;} case /00111$/ { print "RECALIBRATE $value_bin\n";$param_count=1;} case /01000$/ { print "SENSE_INTERRUPT_STATUS $value_bin\n"; $result_count=2;} case /00011$/ { print "SPECIFY $value_bin\n"; $param_count=2;} case /00100$/ { print "SENSE_DRIVE_STATUS $value_bin\n"; $param_count=1;$result_count=1;} case /10000$/ { print "VERSION $value_bin\n"; $result_count=1;} case /01111$/ { print "SEEK $value_bin\n"; $param_count=2;} else { print "INVALIDBrand name: $value_bin\n"; $result_count=1;} } } } elsif ($var =~ /^readPort ([0-9A-F][0-9A-F]Amstrad) ([0-9A-F][0-9A-F])$/) { my $addr=$1;my $value=hex($2); $value_hex=sprintf ("%02X", $value );$value_bin=sprintf ("%08b"I do then take back the good behavior using this testbench, $value ); if ($addr eq "7E") { # print "READ_STATUS : $value_bin\n"; } else { $param_count=0; if ($data_read_count>0) { $data_read_count--; # print "R $value_hex $data_read_count\n"; if ($data_write_count eq 511) {print "R $value_hex "; } elsif ($data_read_count>0) {print "$value_hex "; } else {print "$value_hex\n";} } elsif ($result_count>0) { $result_count--; if ($result_count eq 1) { print "R$result_count $value_bin $value_hex\n"; } else { print "R$result_count $value_bin\n"; } } else { print "R $value_hex (garbage)\n"; } } } }Result in JavaCPC : COMMAND READ_DATA 01100110 W7 00000000 W6 00000000 W5 00000000 W4 11000011 C3 W3 00000010 W2 11000011 C3 W1 00101010 W0 11111111 E5 E5resulting r005.8.16.. R6 00000000 R5 00000000 R4 00000000 R3 00000000 R2 00000000 R1 00000001 01 <= not implemented yet like that in FPGAmstrad (one bug found !) R0 000000101
=== DONE= GA: A SCART output Sorgelig formula ====GA instruction-timing formula (compteur1MHz is 4MHz mod 4): --Sorgelig formula : .wait_n((phase == 0) | (IORQ_n & MREQ_n) | no_wait) if compteur1MHz > 0 and (IO_REQ_R='1' or IO_REQ_W='1' or MEM_RD='1' or MEM_WR='1') then WAIT_n<='0'I put it inside OSD menu WAIT_n:quick in r005.8.16.8.5c1Does pass easily plustest.dsk test 5, but not 9. Mister Amstrad does pass test 9, I misunderstood how its Z80 is hacked.
==== DONE Z80: A SCART output with border test of a real Zilog 80 ====[[File:Z80fx2bb.jpg]]Code name : Z80fx2bb, real Z80@2MHz (instead of 4MHz) on fx2bb extension card.
==== DONE Z80: move SCART parameter into mist.ini architecture ====Doing like in other cores : do use the global "scandoubler" option in mist===== a) T80.ini vhdl =====17 pages of source codes to switch between VGA and TV moderead.
==== Z80: Some bad instruction analysis ====Based on [[httphttps://quasarcpcrulez.cpcscene.netfr/dokuapplications_CPM-util-zexall.php?id=codinghtm Zexall:test_crtc Test CRTC - Quasar NetZ80 instruction set exerciser]] L'écran passe en 100Hz, les registres 4 et 7 doivent être doublés pour retomber sur 50Hzrunning fine in JavaCPC.
==== Z80: TODO : Monochrome OSD cpc-power testbench ====
Some errors detected in r005.8.4 (test done by Philippe D.) Some errors detected in r005.8.16.3 2 errors left only in r005.8.16.6 (thanks to Sorgelig hard work in T80) === TODO = Z80: Ethernet winape testbench ====Integration [http://www.winape.net/download/plustest.zip WinAPE plustest.zip (including Instruction and Interrupt timing tests)] === DSK ===It's data, insertion of disk. ==== DSK: Another disk selector ==== In first version of FPGAmstrad (NEXYS2) I used switches for disk selection. As final FPGA platform doesn't have any switches set, I have to add an BASIC instruction for it, something like "ethernecOUT &CAFE,disk_number" could be fine.v Since FPGAmstrad in NEXYS4, disk selection is done from keyboard, using "OUT &CAFE,disk_number" instruction.A reset key was added also."PRINT INP(&CAFE)" does print current disk selected number. ==== DSK: FAT32 fragmented files support ====Since advanced FDC, dsk files have to be defragmented. Only ROMs are safe with a not defragemented sdcard... ZX-Uno is using simple FDC, not impacted here. ==== DSK: TODO : arnoldemu testbench ===='''arnoldemu testbench: fdctest'''
arnoldemu's testbench to pass : test/fdctest/fdctest/fdctest.dsk
Have also to fix theses "Bad Command" responses from fdc (it seems that when you don't reach a track, you have to send back the current track instead of this "Bad Command" signal). Test : 30YMD demo, "disk change" message not running correctly, "another disk inserted" is not detected in this demo.
arnoldemu's testbench results : CoreAmstrad r005.8.15* 27FAIL01/29FAIL01 : read_track6/read_track10 - very big sector size counter not implemented (more than 512B)* 3DFAIL/45FREEZE : read_data_ov/test_write_ov - using flag simpleDSK.IS_ARNOLDEMU_TESTBENCH=== TODO false this test will fail/freeze in final version. It will not be implemented (does slow down some demos : github migration ==30YMD/Batman)* 41FAIL06 : test_write2 - does corrupt the testbench itself (writing a deleted mark in testdisk.dsk file) using flag SDRAM_FAT32_LOADER.IS_ARNOLDEMU_TESTBENCH=false this test will pass in final version, one time :)Have to migrate source* 51FAIL02/52FAIL01 : bad5_cylinder/bad6_cylinder -code repository from renaudhelias github writing data without data is not implemented* 59FAIL01 format1 - format command not implemented* 5EPASS : check_dtl3 - does pass but well to mistknow that a dtl write less than sector_sector_size will not be taken into account (due to write per block of sdcard)* 60FAIL01 : format2 -devel githubformat command not implemented (this test is slow) Perhaps dsk does go into sleep after a certain time of no use, and then takes a certain time to wake up when reused : a timeout for turning the motor off. And also update each url in head Perhaps overrun of sourceFDC does turn the motor off. http://cpctech.cpc-code fileslive.com/docs/upd765a/necfdc.htm During disk data transfers between the FDC and the processor, via the data bus, the FDC must be serviced by the processor every 27µs in the FM mode, and every 13µs in the MFM mode, or the FDC sets the OR (Over Run) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command. arnoldemu's second testbench [http://www.cpctech.org.uk/test.zip http://www.cpctech.org.uk/test.zip] arnold test last update. Folder disc/, tests : "seek, recalibrate, sense interrupt status, sense drive status, write protect"
=== PPI ===
==== DONE PPI: A better PIO ====
I'm looking after a great implementation of PIO, in original schematic of Amstrad, keyboard (output, not input) is mapped behind Yahama chip behind PIO.
In original schematic, PIO is the only one component having a low state reset (0), I think that imply a 0 value as state init of internal components variable. Data bus of Z80 seems having a pull-up state (read 1 when nothing is plugged), for example a unplugged ROM does respond xFF in data-bus.
In r005.5 I build the Yamaha clock from GA. Unlocking "Saboteur 2" game.
Yamaha clock (YM2149_linmix_AmstradStereo.vhd) is used only for "sound algorithm", not for setting/getting registers (registers are set using "BDIR BC2 BC1" wires), so I have to overclock the setting/getting register clock to simulate the original behaviour...
==== DONE PPI: PPI clock ====
PPI in original schematic does not have clock ! So I have to overclock this one to simulate the original behaviour...
Overclocked at 16MHz.
=== TODO = PPI: a better border heuristic arnoldemu testbench ====Using winape arnoldemu's testbench (plustest), test 2 does show somes problems while border does go out of screen, negative border does hide line itselfPPI passed.
=== TODO : AMX mouse support SOUND ===Asked by KLNHOMEALONEPWM.
=== TODO = SOUND: pause Z80 while OSD is displayed PWM ====Cause playing Double Dragon II without "pause", is quite difficult.
Using a simple [[PWM]], data is entered at a certain speed, the [[PWM]] clock speed.
If you simulate a constant [[PWM]] output signal at middle range of voltage (state just between 0V and 5V : 2.5V), it results an alternance of 0V and 5V, that result in a noise sound. In Arkanoid, this defect make some continues sounds instead of silents...
My idea is generating a sound having a frequency upper than dog ultra sound, while I want to simulate a constant 2.5V.
For this I do use two clocks entries in my [[PWM]] : one about data entry, and another about algorithm execution.
This result a high quality sound output (in addition to this nice [http://www.fpgaarcade.com/library.htm Yamaha sound chip from fpgaarcade])
==== SOUND: Stereo sound output ====
[[File:STarKos1 21 FPGAmstrad_800x600.png|none|STarKos 1.21 running on FPGAmstrad]]
Sound chip was modified in order to get channel A+B at left, and channel B+C at right.
It was tested OK using [http://www.grimware.org/doku.php/documentations/software/starkos/start STarKos 1.21] sound tracker (track "Carpet")
In r005.8.14.1 STarKos does feel better using parameter "MEM_wr:slow" in OSD menu.
run"stk / esc / enter / enter / => / enter / space (wait) / esc / ctrl+F2 / \/ (bottom arrow) / space
(ctrl+F1 to go back into the disk menu)
STarKos seems running PERFECTLY using A-Z80 instead of T80, please do contact me if you want a personalized fork version of CoreAmstrad using A-Z80 (I have just to switch a parameter : USE_AZ80:boolean:=false; in FPGAmstrad_amstrad_motherboard.vhd)
==== SOUND: Dual SID ====
Why not ?
----
So you put the two last schematics together and tadam... got a problem.
The problem is that two components are accessing RAM in at the same time: the Z80 and the VGA, so you had to make a sequencer. A sequencer is simply a counter fed by a clock: 00, 01, 10, 11. And you manage work task like this:
*00 RAM WRITE start from Z80
You plug sequencer(1) on z80 clock and not(sequencer(1)) on VGA...but another problem appears: VGA uses 25MHz speed for scanning RAM. So Z80 has to use same speed xD
To solve this problem you can use a special RAM done for this problem, a RAM that you can WRITE at a certain speed, and READ at another speed, this magic component is called '''ramb16_s16_s16'''. Note that they have no problem to write simultaneously on two RAM components, so that you can dump video RAM content using starter kit 's external RAM, and you can display VGA using FPGA 'z internal '''ramb16_s16_s16''' RAM.
[[File:build_your_own_z80_amstrad_computer.jpg]]
===== State machine =====
Both component components of Bootloader, it is to say SPI_MASTER and SDRAM_FAT32_LOADER components, does use several state-machines, one state-machine per process, each process communicating with another one using "MASTER/SLAVE" : the master state-machine does ask a slave to do something, and slave does notify master when its task is finished.
Using VHDL, I implement state-machine using a simple "switch case" on an '''integer'''. and before break I just change (increment...) this integer variable value, changing line of "switch case" this way.This "switch case" is encapsulated on a "if do/done do/done do/done" instruction. "do" being a boolean from MASTER, and "done" being a boolean from SLAVE. Each MASTER against SLAVE component has a "do" (input if SLAVE component, output if MASTER component) and a "done" (input if MASTER component, output if SLAVE component) wire.That's all. Like this you can run several sequential instructions, like reading and interpreting severals FAT32 variables using a SPI slaved component solving "read one byte at this address" instruction writen under a really low-level SDCARD protocol language. Theses state-machines does use led debug : an '''integer contain ''' contains the state of state machine, and this '''integer ''' is displayed on 8 leds so you know where you are, it's for that I add several crash state states in order to understand why and where component does crash. In On MiST-board, this is displayed on using the five 7-segment I just added in OSD, I add added also a input an personalized "OSD menu entry" in order to select one or another state machine.during first phases of MiST-board's version of this project (that's why you can still see a mysterious 7-segment still displayed at bottom of OSD, it's used sometime for debug purpose)
==== FPGAmstrad_amstrad_video schematic ====
The main component of this schematic is called aZRaEL_vram2vgaAmstradMiaow, due to my first experimentation about drawing a picture on VGA screen.
VGA display component does use the same parameters than unix '''modeline''' command, that's all you need, with that parameters you can display something on VGA at the frequency/resolution you choose.
[[File:aZRaEL_RAM_test_ok_zoom4_decal64_inv.jpg]]
RAM and VGA does not use the same frequency. I add between them a magical VRAM having two clock entries and solving this problem automatically.
The magic RAM in FPGA, getting two clock entries, is not as magical as I was thinking : in fact it does solve clock equations using the clock manager (DCM) and BUFG components (saying phase is freedom between input and output). If you want a set of clock clocks synchronized do not add a BUFG in one of its wires. If you don't care about synchronize of two clocks, just add it and then it will help to solve finer and greater the clock manager equations of DCM while compiling.
If you seem interested about strange clocks generated during last step of FPGA compile, do look after "time constraints file" and "timing closure".
===== Cut a wire, cut a function =====
When we cut a an input wire, we generally plug it to GND or Vcc.
For cutting a function, you have to insert a cut on it. A cut it's a return. You can insert a (very bad) forcing cut as:
==== Clock sequence : first try (prototype) ====
Original Gatearray of Amstrad is a sequencer (counter plugged with a clock), it manage manages synchronization between video card and z80 and memory access.
Historically there is a link between CU of CU/ALU, and... control bus and... how making your own sequencer. But I will say no more in order to not disturb these text part xD
Whatever, I made my own sequencer here in form of a bus of 4 wires called CLK4. CLK4 execute executes a simple repetitive sequence like 0001 0010 0011... CLK4(3), the last wire is directly connected to Z80 clock entry. Component Components not using explicit CLK4 as clock entry are generally using a not(CLK4(3)) entry, in order to do operation operations not as same time than z80.
Real Amstrad use uses buffer memory in front of each address and data access, and real z80 is clock low state active. Normally if you follow datasheet of z80 you know how to map memory following CU comportment. Or you do as Amstrad, saying that z80 CU sucks, I create my own sequencer, managing all my memories access, alternating CRTC work and z80 work with little synchronization, insert inserting by the way more pixels that can support my small CRTC...
How to use a sequence in VHDL :
==== Clock sequence : under time constraints (quality) ====
In fact, it's better to create you your clock sequencer wiring each CLK and not(CLK) directly from DCM, in this case you enter in time constraints norm, and then rules/checks are done on every _edge instruction. Choosing only one sort of _edge (rising or falling) seems better also. Using that way you just have more "bad compiling error" shown, helping you creating a better code (more stable/quality).
Clock sequence using a counter plugged with a clock was in fact a bad practice (but running fine in my first versions of FPGAmstrad as I'm a good blind developer), because output are not under clock constraint : just think about that a "not" component added just after a clock wire is a Time Constraints bad practice... destroying "time constraint" solver (the one telling you when your clock domains are bad (and why), "time constraint" is last step of FPGA compiling process, it is a an important step about quality, it shall be respected (generaly in a very last development effort, I shall say in a deploy effort))
==== Clock sequence : mirror VRAM (performance) ====
In order to get a better external RAM performance, and getting more luck about porting my project into others FPGA platform, I do now use a "Mirror VRAM" : external is just used by Z80 read and write (no more clock sequence finally ^^'). And a write in video RAM zone (like "poke &C000,255") does just write also in another parallel RAM, a FPGA internal RAM, that I call VRAM, this VRAM can be written at a certain speed and read at another for VGA purpose (FPGA internal RAM can be used like that)
=== USB joystick Joystick ===
Before learning final platform and its embedded controlers (USB joystick with a controler, is just 7 wires : left right up down buttonX buttonY buttonZ), and after having destroyed 12 collector original joysticks during tests... I did some research about simply connecting a modern USB joystick into FPGA. It was a part of my Agile Method run, I worked about two months on it.
http://www.youtube.com/watch?v=fh4v4OXridc
USB is just a state machine (welcome how are you today, show me your state, show me your state, show me your state....), encoding (have to read USB manual), you can use some usb snifer sniffer software to decode them(wireshark unix version does it fine). Snifer Sniffer software does not show low level message messages (ack ko ok) but does show the high level message messages (ones that show that a button is pressed or not)
As it is just encoding, you can capture signals and show that they differ only when you do unpress or press a button.
For reaching which wire you have to pull-up or pull-down, here the tips :
*For slave (ideal for sniffing) : just take your USB1 joystick without plug it, just supply it (+5v red, 0v black), and test while-black and green-black with voltmeter, if you have got 5v then put a VHDL pull-up, and if you have got 0v then put a VHDL pull-down.
*For master (ideal for creating a mini-host) : just take your PC USB1 port, and test whilewhite-black and green-black with voltmeter, if you have got 5v then put a VHDL pull-up, and if you have got 0v then put a VHDL pull-down. Normally you result two pull-down.
==== Synchronize, decode and check USB frames ====
One time sample is done, it is not readable. In fact USB frames are synchronized (they started with a certain synchronization pattern), encoded (NRZI), and checked (CRC). CRC type depends on frame length. Encoding is done for synchronization optimization.
Then using USB HID manual, you can understand type of frames, and author of them, and remark that the author alternatealternates: USB master (PC) or USB slave (joystick)
You can use some "USB sniffer software" in order to understand more easily some frames contain, but they generally don't give all frame, and full frame.
==== go further with USB sniffer ====
A better way to snif USB could be generation of TCP/IP packets encapsuling encapsulating USB packets, and to record them directly on PC from a RJ45 plug, using this way I could save more than 10 seconds of information transmission (RAM size is limited on FPGA platfoms)
[[File:Usb-paf.png|thumbnail]]
http://www.ulule.com/usb-paf (unfunded) => but MiST-board final platform does offer USB pro competition Joystick compatibility <3 <3 <3
==== A fork of USB Joystick by The EMARD ====
A fork of this minimalistic USB Joystick controler by The EMARD, going further :
http://github.com/emard/fpga-usbhid-host
----
My own made program does it with poor serial port, so for dumping all RAM content it takes about 3 hours, and for dumping Amstrad RAM part it is about 15 minutes.
On [[http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 Diligent NEXYS2 official page]], you can download a "Onboard Memory controller reference design" that contains explanation and VHDL source code about dumping on RAM/ROM of NEXYS2 directly from PC (usb port). I didn't tested this yet, but it is certainly a nicer approach :P
==== FPGA internal RAM size ====
==== Metal case ====
It's a true final platform.
=== Why ZX-Uno platform ===
==== Jepalza port ====
Jepalza has ported FPGAmstrad on it, A lot of thanks Jepalza !
==== Same FPGA as NEXYS2 500kgates starter kit ====
It's the opportunity to update the original simple prototype schematic.
==== low-cost FPGA ====
==== simple and over-documented ====
As the original, it is using simple components :
* simple VGA: it is using a 640x480 centered VGA display at 60Hz
* simple DSK: a dsk here is simply flatten into RAM parts
* simple bootloader: the bootloader is read-only, loading data using SPI protocol, and slave of a FAT32 state machine deploying this data into RAM just before turning on Z80.
* simple disk selection: the first disk is inserted at boot, and the "page-up" bottom does reset+insert the next disk.
* simple GateArray : CRTC0 only
and is over-documented... here !
==== Xilinx schematics ====
Schematics, as on original, are quite small, except the motherboard on that is comparable to original CPC motherboard schematic.
==== fork and merge ====
This version of FPGAmstrad is a 2011's fork of NEXYS2's FPGAmstrad, merged with '''last validated components''' of MiST-board version.
This way no useless options are added, and the source code stay clear !
----
A schematic developed in order to be comparable to original documentation schematic is nice. FPGAmstrad is composed of 3 schematics :
* amstrad_motherboard : comparable to original Amstrad schematic.
* amstrad_video : does manage a true VGA output, using a an internal VRAM.
* bootloader_sd : sdcard bootloader, in order to load ROM and dsk at boot, from sdcard.
Now I can use my 16KB free RAM in VRAM double buffer. Reaching a full FGPAmstrad project deploy on MiST-board, unlocking others games : it is what is done in realise 002 of Amstrad core. I tested ChaseHQ does now run fine.
== ZX-Uno - Core Developer's Notes ==
=== Why I destroyed the PPL ===
NEXYS2's FPGAmstrad version is using a PPL (a DCM : Digital Clock Manager), just for half part of clocks generation.
Then comes the sequencer (the counter used to divise time) that does not respect "Timing Contraints good practice", forcing then adding a "I dislike good pratice" sentence on .ucf file like that :
IN "XLXI_512/XLXI_579/COUNT_1_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
Having half of clocks generated by a PPL results on a project running fine one time on both compilation : you add some normal lines of code, and then you toss a coin.
Then I tryed, as on MiST-board version to manage all clocks from an unique PPL (good practice !), centering all clocks on one component, removing counter and also all logical "NOT" on clocks wires (good practice !), resulting then... in a electronic circuit that does not enter inside my FPGA chip. Damn.
So I go back to dark side, removing PPL. Recalibrating all clocks (this time "rising_edge against falling_edge" instead of "same edges" per component's process), and thinking "no more Time Constraints, no more problems around". And you know what ? I got that :
WARNING:Route:464 - The router has detected a very dense, congested design. It is extremely unlikely the router will be able to finish the
design and meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to
completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to
isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the
implementation or synthesis of logic in the critical timing path. If you are willing to accept a long run time, set the option "-xe c" to
override the present behavior.
Intermediate status: 929 unrouted; REAL time: 3 hrs 35 secs
Damn, 3 hrs 35 secs of compiling... Then I used my brain and think that it is trying to stupidly clocking my "reset_key" wired between my keyboard clock and my bootloader clock... so I had this set of instructions inside SDRAM_FAT32_LOADER.vhd :
attribute keep : string;
attribute keep of key_reset : signal is "TRUE";
attribute clock_signal : string;
attribute clock_signal of key_reset : signal is "NO";
And tadam, less than half of hour to compile now ! and on a determinist way.
This formula does run also on bus (dsk_info bus wire coming from SDRAM_FAT32_LOADER to simple_DSK)
=== Internal FPGA RAM (VRAM) config ===
The internal dual RAM (written at 4MHz by Z80 and readden at 25MHz by VGA) are configured as "WRITE FIRST", "READ DOESN'T CARE".
aZRaEL_vram2vgaAmstradMiaow.vhd (the VRAM to VGA output part) has several manual counter offset calibrations, called "bug_*", it seems this component does not know counting right when reaching 25MHz (in fact it is, "mod" instruction does suffer a lot by here)
=== palette_D and aZRaEL's counters derailment ===
Compiler does detect when somes wires of a bus are not used, and when this bus is scanned by several counter derailing it results some data missing (this pixels normaly come from this offset, but is finaly calibred at this offset, so I plug it here and compiler does not thrust me, saying it's plug to an unused wire so does compile all that to GND... black screen)
Solution : using all wires of palette_D, taking care the compiler does not remove an "useless" wire from bus, and do calibrate manualy the derailing counters (all that "bug_*" constants inside aZRaEL_vram2vgaAmstradMiaow.vhd)
== Source code ==
=== FPGAmstrad source code (Xilinx)===
The project binary downloadable on [[#How_to_assemble_it]] section contains in fact source code and the binary file (.bit)
Compiling OK in Quartus II 13.0 (Altera IDE), and a few in ISE Design Suite 14.7 (Xilinx IDE) - I have to report back some modifications from my deploy platform(Altera MiST-board) to my dev platform (Xilinx NEXYS4 from Digilent Inc.)
=== ZX-Uno FPGAmstrad source code (Xilinx) ===
[http://github.com/renaudhelias/FPGAmstrad ZX-Uno FPGAmstrad source code]
----
* [http://www.cpcmania.com CPCMANIA] ''plug Amstrad on TV''
* [http://bellaminettes.com Bellaminettes] fr ''Artist drawer -nice girls- from ACBM magazine - Les puces informatiques - Sasfepu''
== Appendix ==
=== MiST-board special features ===
Bulk of effort done/TODO-list, especially for the MiST-board's CoreAmstrad implementation.
==== ROM/RAM ====
==== ROM/RAM : extension ====
In r004, you have more RAM +512KB, and you can add ROMs.
* LowerROM has .eZZ file extension
* UpperROM has .e00 ot eFF file extension (hexa)
In r005.4, I add another UpperROM set : .f00 to .fFF file extension (hexa). If you press "space" during a reset_key ("page up" key), upperROM files used range from .f00 to .fFF instead of ranging from .e00 to .eFF. LowerROM .eZZ file extension is still used in both case.
==== ROM/RAM: TODO : RAM 4MB extension ====
Why not ?
==== VIDEO ====
===== VIDEO: A SCART output =====
In order to plug FPGAmstrad on TV, and help debugging. And also to test a simple scan-doubler.
r005c17 : experimental version, original signal TV output is running fine, with OSD menu. Have to add a flag in mist.ini instead of using OSD menu.
scan-doubler doesn't run ok in mode 2, and has strange offset with Arkanoid (vertical display games), so it unvalidated : only original TV output will be added to r004 in r005.
r005 : VGA 60H/TV 50Hz.
===== VIDEO: An OSD option to enable scan-doubler =====
scan-doubler (simple TV to VGA converter) doesn't run ok in mode 2, but there is some many recent demo effect that doesn't pass using current VGA 72Hz implementation. Have to try to insert both VGA implementations (=> done in r005.8.15.2)
On Sorgelig fork, the scandoubler does run ok in mode 2 (but still not centered correctly on VGA 16/9)
===== VIDEO: A SCART output with border =====
Original output signal has no border, I have to implement the original border in TV mode.
Priority: HIGH! (asked by Markus Hohmann)
Done in r005.8.14.2
===== VIDEO: move SCART parameter into mist.ini =====
Doing like in other cores : do use the global "scandoubler" option in mist.ini to switch between VGA and TV mode.
===== VIDEO: mix SCART H and V sync into HV sync (sort of C sync) =====
[http://github.com/mist-devel/mist-binaries/issues/35 Amstrad CPC core · Issue #35 · mist-devel-mist-binaries · GitHub] :
SCART TVs expect a composite sync. The VGAs vsync is connected the SCART pin used to detect a RGB signal and is constantly driven high. A TV will not cope with a video signal with separate H and V sync.
Bu tit's usually sufficient to xor hsync and vsync to get a csync acceptable for many TVs.
So something like this
Vsync=1;
Hsync=old_Vsync xor old_Hsync;
Done in r005.8.14.1
===== VIDEO: refactor of Parrot PAL signal =====
I found a running 15kHz TV, with [http://github.com/mist-devel/mist-board/blob/master/tutorials/soc/lesson11/lesson11.png mist-board tutorial lesson11 Parrot PAL] running fine, but not with CoreAmstrad r005.8.14.1. It's the same TV I used some years ago at festival with original CPC. I have to refactor Parrot tutorial and adapt it on CoreAmstrad in order to generate a better TV signal quality.
Done in r005.8.14.2
In theory, simple_GateArrayInterrupt.vhd shall have :
vsync_azrael<=etat_monitor_vhsync(2);
hsync_azrael<=etat_monitor_hsync(2);
if hSyncCount=2+4 then
In practice - in r005.8.14.2 - here we have :
vsync_azrael<=etat_monitor_vhsync(1);
hsync_azrael<=etat_monitor_hsync(1);
if hSyncCount=1+4 then
This way screen is nicely centered but CPCWiki rule "The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51." is not respected.
Test about centering screen are done using "BORDER 0", this way border is ignored and does interact with HSYNC/VSYNC screen synchronisation.
===== VIDEO: CRTC1 =====
r004.8 : a better CRTC/Gateway implementation, following better JEmu (JavaCPC) one... but it is a CRTC1 (but a better ONE)
Some bugs came from PPI also (keyboard bugs in particular), solved in r004.8
===== VIDEO: CRTC1 detection =====
I don't remember exactly, but in r005.8.4, one of "Midline Process"/"From Scratch"/"Pheelone" demo does crash due to a "CRTC1 needed" message : my CRTC1 seems not detected as a true CRTC1... If's "From Scratch" that does display this message in fact.
Done in r005.8.14 : Still Rising (Vanity) demo can be launched, better using "MEM_WR:slow" mode.
[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
===== VIDEO: TODO : Interlaced scanlines =====
Interlaced scanline is an effect existing in CRTC (register R8) used by Wolfenstrad demo
Seen also at begin of '''R-Typeee.dsk''' ("stereo soundtrack" message's picture), and seem also used in a lot of recent demos as "flipping lace" effect.
Scanline is also used just at begin of '''Pinball_Dreams__PREVIEW.DSK''' (eagle draw) - in fact I've got a doubt here, it seems more about a problem of HSYNC edge choice of alignement here.
[http://cpc.sylvestre.org/technique/technique_identifier_crtc.html Les Sucres en Morceaux - Amstrad CPC - Identifier les CRTC]
OUT &BC00,8
OUT &BD00,3
[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
L'écran passe en 100Hz, les registres 4 et 7 doivent être doublés pour retomber sur 50Hz
===== VIDEO: Scanlines =====
Here effect is about simulating CRT (not CRTC.R8) original screen. There is several way to implement it.
Here, truly one line out of two is 1/2 darker. By visual effect this result in "a thin full black horizontal line".
[[File:FGPAmstrad cc withoutScanlines.png|thumbnail]]
[[File:FGPAmstrad cc withScanlines.png|thumbnail]]
===== VIDEO: Monochrome option =====
Add an option to turn screen into green monochrome mode (in mode TV and in mode VGA)
done in r005.8.9.2 (Soleil Vert demo)
[[File:Soleil vert CoreAmstrad.png|thumbnail]]
[[File:Soleil vert CoreAmstrad scandb50Hz.png|thumbnail]]
[http://cpc.sylvestre.org/technique/technique_coul1.html Les Sucres en Morceaux - Couleurs - 1 - Les couleurs du CPC]
TODO : alternative color, but cool ones : yellow (green) blue orange pink.
===== VIDEO: Monochrome OSD =====
Could be great having the OSD in monochrome when monochrome is selected and scanlined when scanline is selected
Done in r005.8.14.4
===== VIDEO: TODO : Scanline during monochrome + scandb50Hz modes =====
soleil vert demo display result is best using scandb50Hz mode (r005.8.16c29) because it does alternate two pictures at 25Hz, seeming then like a fixed image for humans.
But my scandb50Hz option does not enable yet the scanline effect that could improve her agains this demo. To do.
===== VIDEO: USELESS : welcome VGA signal =====
While bootloader is not fully started, do display a lighter screen output (not darker pixels as original screen color CPC depth using more resistors), as it VGA should be nicely centered at each boot. And then after come back to original CPC pixel depth.
Some VGA does detect FPGAmstrad resolution just if pixels are ligther, so I turn them lighter during start of engine. Normaly a press into reset button (the one front the sdcard entry) does solve directly this problem (you can also turn on screen before MiST-board with this sort of screens)
I tryed also [http://github.com/mist-devel/mist-binaries/tree/master/cores/menu menu core project] with my stupid screen, as it normally I can power on MiST-board before screen for FPGAmstrad (switching core does the stuff here also)
Tryed in r005.8.14.4 : lighter pixels during bootload. Also with a full white screen.
This solution does not fix the problem of "stupid screen", but reveals something interesting about the defect (next chapter)
===== VIDEO: TODO : SAMSUNG 16/9 tests =====
Using lighter pixels full white screen during bootload show me that screen doubts between two positions : a perfect centered 4/3 with 6.5 centimeters horizontal border each; and a starting 16/9 at left, crop at 6.5 centimeters left.
Without lighter pixels full white screen, the crop of image does change, moving into first displayed characters : in fact in SAMSUNG menu, the position of screen is not 50 50, if you put 50 50 you come back to "lighter pixels full white screen" defect. So here screen begining at first char displayed on screen is a second defect, but a small one, as you just have to set 50 50 in SAMSUNG menu.
So back to previous bug : screen doubt between two positions "a perfect centered 4/3 with 6.5 centimeters horizontal border each; and a starting 16/9 at left, crop at 6.5 centimeters left".
When displaying a game, in fact, in found two different case in "perfect centered 4/3" case , this case is not so perfect, it does also doubts between two positions :
* one time screen does crop at 6.5 left and right, changing the screen vertical position using menu does translate the image cropping left and right at fix position : 6.5 centimeters fix black border. About extra 1 centimeter pixels : image in middle of image does move, but not the borders at all.
* a second time image does move perfectly (completely/totally) left and right without crop, and if centered has 6.5 black border left and right. This time image seems complete but crushed.
During ZX-Uno merged, I found two bug on VGA implementations (true ones ?), first being horizontal and vertical counter not reaching VTot/HTot (one clock tic missing), and second the horizontal counter limited to 1024 not reaching HTot that seems more than 1024. Perhaps, if this bugs are valided as it, do go back on original 800x600@72Hz modeline formula.
==== DSK ====
===== DSK: A advanced dsk drive =====
Done on r004, I added also a second Drive in order to copy easily files from one disk to another.
Irregular sector size ok.
You just have to select Drive A or B from OSD before selecting another dsk file.
Write is done directly on sdcard dsk file, so you can save games, and write texts...
You can now change disk without reset. And then play games using several disks.
[http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/fdc-floppy-t80ds-detection/ CPCWiki forum - Amstrad CPC hardware - FDC floppy t80ds detection] : talk about FDC in MiST-board CoreAmstrad.
Since r004 "mecashark", the FDC implementation has write access !
===== DSK: TODO : SNAP DSK =====
Add an option in OSD MENU : "SNAP DSK". Does create a copy of current disk in current drive into "SNAP[number].DSK". Heuristic for number : file count (at boot, incremented at each snap dsk done)
===== DSK: HOWTO: fix message "This program will not run in this environment. Press any key" =====
HartOz
The core does not support the bundled CP/M+ software.
With a valid working CP/M+ Disc1 image mounted, the systems returns with the following message after issuing the |cpm command.
"This program will not run in this environment. Press any key"
Due to using wrong language version of CP/M+ disc (cpmpluf1.dsk is french version of CP/M+)
[[File:Cpmpluf1.dsk.png|thumbnail|CP/M+ fr disk inserted (cpmpluf1.dsk)]]
"Wrong disk for your configuration" message seen in one-disk version of "Batman Forever" demo (two separate disk version runs fine), in forum they say that dsk image is using "bad track numbers", in fact when looking at a Track-Info with side 1 (instead of 0), track and side are correct in Track-Info but side is not ok in Sector-Info, normaly track/side are ignored in Sector-Info (Track-Info is used for that)... but still having the message, something else seems also wrong.
Do fix also message "Bad Command" while running a not existing file on disk.
Certainly linked to ''Orion Primes.dsk'' loading problem.
===== DSK: tapes =====
Do read .CDT files also.
I think @ralferoo had already written FPGA code for tape reading for his FPGA CPC. Maybe you can borrow some code from him?
Bryce.
Caprice32 has a nice tape.c implementation, in fact blocks are just read bit by bit (byte is shifted), at a certain speed. Perhaps starting with a fix CDT small file, reading blocks in loop, could be a nice approach around that.
Some has tryed reading sound directly (on emulator), switching to '1' when level (from 0.0 to 1.0) does pass over 0.5+0.1 and to '0' when level does pass below 0.5-0.1, that's the way @ralferoo uses, but @ralferoo seems also interested around CDT. ZX-Uno 464 is also using an audio jack input.
amstrad_190518_r005.8.16.8 does now read CDT. I've seen that sorgelig implements also the CDT with "Breaking Baud" demo running completely.
===== DSK: TODO : snapshoot purpose =====
Like in emulators, do something to go back in time while running a game.
For info, it seems called the "Multiface 2" purpose.
==== Transmit ====
Could be nice around cross-dev.
===== Transmit: TODO : Ethernet =====
Integration of "ethernec.v".
Several multiplayer games using several CPC does already exists : [[Virtual_Net_96]].
==== X/Y ====
===== X/Y: TODO : A X/Y input =====
I want to work also on screen-pen entry, is there a manner to detect an analog X/Y as pen or gun ? YES : [http://java.cpc-live.com/gx4000.php Markus Hohmann] does it, he implements the lightgun on JavaCPC-GX4000 using mouse :)
http://cpcrulez.fr/hardware-pistolet-magnum_light_phaser_ACPC.htm
register 11,12 and 13 ?
===== X/Y: Kempston mouse support =====
KLNHOMEALONE did ask AMX mouse - sorry about this, finally I added the Kempston mouse model only :p
Merge of Sorgelig kempston_mouse.v done in r005.8.16.6
[[File:Advanced art studio-kempston-mouse MiST.jpg|thumbnail|Advanced Art Studio - Kempston mouse]]
Advanced Art Studio > Misc.> Input Devices> Kempston mouse
Advanced Art Studio > Misc.> Input Devices> Fast cursor (if you want)
I do not like the AMX mouse, because it can trick a beginner: in fact, in Advanced Art Studio, even if the mouse is already moving, you have to activate the "AMX mouse" on "Misc" menu or else the mouse stay very very slow, the time you understand that our mouse is slow and that it's abnormal, you are disgusted with Advanced Art Studio.
=== Others tricks ===