Changes

Gate Array

In the CPC+ system, the functions of the Gate-Array are integrated into The gate array is a single [[ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array specially designed chip exclusively for use in the Amstrad CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new featuresand was designed by Amstrad plc.

In the [[KC compact]] CPC+ system, the functions of the Gate-Array are "emulated" in integrated into a single [[TTL logicASIC|ASIC]] . When the ASIC is "locked", the extra features are not available and by the [[Zilog Z8536 CIO]]ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the "cost-down" version of the CPC6128[[KC Compact]] system, the functions of the Gate-Array are integrated into a ASIC"emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

The In the "cost-down" version of the CPC6128, the functions of the Gate -Array is described here, as it is in are integrated into a standard CPCASIC.

== Controlling the The Gate Array ==is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.

The gate array is controlled by I/O. The gate array is selected when bit 15 of == Controlling the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".Gate Array ==

The recommended gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is &7Fxxset to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.  The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.

|0''Data Bit 7''||0''Data Bit 6''||Select pen''Function''

|0||10 ||Select colour for selected pen

|10 ||01 ||Select screen mode, rom configuration and interrupt controlcolour for selected pen

| 1 || 0 || Select screen mode, ROM configuration and interrupt control|-|1||1||Ram RAM Memory Management (note 1)

===== Note ===== This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464,CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K Ram Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a PAL located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on Ram Management for more information.

When bit 7 and bit 6 are set to "== Register 0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.Palette Index (Pen selection) ==

The When bit 7 and bit 6 are set to "0", the remaining bits determine which pen remains is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected until another . When bit 4 is chosenset to "1", the value contained in bits 3-0 is ignored and the border is selected.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pensThe pen remains selected until another is chosen.

|7''Bit'' ||0''Value'' ||Gate Array function "Pen Selection"''Function''

|67 ||0||rowspan="2" | Gate Array function "Pen Selection"

|56 ||x||not used0

|45 ||1- ||Select bordernot used

|34 ||x1 ||ignoredSelect border

|23 ||x||ignoredrowspan="4" | Ignored

|12 ||x||ignored

|01 ||x||ignored

|7''Bit'' ||0''Value'' ||Gate Array function "Pen Selection"''Function''

|67 ||0||rowspan="2" | Gate Array function "Pen Selection"

|56 ||x||not used0

|45 ||1- ||Select pennot used

|34 ||x0 ||Pen numberSelect pen

|23 ||x||rowspan="4" | Pen number

|12 ||x||

|01 ||x||

==== Register 1 - Palette Data (Colour selection ==) ==

Once the pen has been selected the its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

===== Summary == ===

|7''Bit'' ||0''Value'' ||Gate Array function "Colour selection"''Function''

|67 ||10 ||rowspan="2" | Gate Array function "Colour selection"

|56 ||x||not used1

|45 ||x- ||Colour number xnot used

|34 ||x||rowspan="5" | Colour number x

|23 ||x||

|12 ||x||

|01 ||x||

==Register 2 - Select screen mode and ROM configuration == Hardware colour palette  This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration.  ===Screen mode selection === The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

|19''Bit 1'' ||Bright Cyan''Bit 0'' || ''Screen mode''

|200 ||Black0 || Mode 0, 160x200 resolution, 16 colours

|210 ||Bright Blue1 || Mode 1, 320x200 resolution, 4 colours

|221 ||Green0 |-|23||Sky Blue|-|24||Magenta|-|25||Pastel Green|-|26||Lime|-|27||Pastel Cyan|-|28||Red|-|29||Mauve|-|30||Yellow|-|31||Pastel BlueMode 2, 640x200 resolution, 2 colours

This Mode changing is not an official colour synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

Select screen mode and rom === ROM configurationselection ===

This Bit 2 is a general purpose register responsible for used to enable or disable the screen mode lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the rom configurationRAM.

==== Screen mode Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection ====]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

The function of bits 1 and 0 is to define Bit 4 controls the screen modeinterrupt generation. The settings for bits 1 and 0 and It can be used to delay interrupts. See the corresponding screen mode are given in the table belowdocument on interrupt generation for more information. === Summary ===

|0''Bit'' ||0''Value'' ||Mode 0, 160x200 resolution, 16 colours''Function''

|07 ||1||Mode 1, 320x200 resolution, 4 coloursrowspan="2" | Gate Array function

|16 ||0||Mode 2, 640x200 resolution, 2 colours

|15 ||1- ||Mode 3, 160x200 resolution, 4 colours (note 1)not used

This mode is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has == Register 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours.- RAM Banking ==

Mode changing is synchronised This register exists only in CPCs with HSYNC. If 128K RAM (like the mode is changedCPC 6128, it will take effect from the next HSYNC. ==== Rom configuration selection ==== Bit 2 is used to enable or disable the lower rom areaCPCs with [[Standard Memory Expansions]]). The lower rom area occupies memory addressess &0000-&3fff and is used to access Note: In the operating system rom. When the lower rom area is is enabledCPC 6128, reading from &0000-&3FFF will return data in the rom. When a value register is written to &0000-&3FFF, it will be written to the ram underneath the rom. When it is disabled, data read from &0000-&3FFF will return the data in the ram. Similarly, bit 3 controls enabling or disabling of the upper rom area. The upper rom area occupies memory addressess &C000-&FFFF and is BASIC or any expansion roms which may be plugged into a rom board/box. See the document on upper rom selection for more details. When the upper rom area enabled, reading from &c000-&ffff, will return data in the rom. When data is written to &c000-&FFFF, it will be written to the ram at the same address as the rom. When the upper rom area is disabled, and data is read from &c000-&ffff the data returned will be the data in the ram. Bit 4 controls the interrupt generation. It can be used to delay interrupts. See separate [[PAL16L8|PAL]] that assists the document on interrupt generation for more informationGate Array chip. ===== Summary =====

|7''Bit'' ||0''Value'' ||Gate Array function ''Function''

|67 ||1||rowspan="2" | Gate Array function 3

|56 ||x||not used1

|45 ||xb ||Interrupt generation controlrowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]

|34 ||x||*1 Upper rom area disable*0 Upper rom area enableb

|23 ||x||*1 Lower rom area disable*0 Lower rom area enableb

|12 ||x||Mode slectionrowspan="3" | RAM Config (0..7)

|01 ||x||

Defining The 3bit RAM Config value is used to access the colourssecond 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, <br>Setting pen which are selected with bit 3-5. A standard CPC 6128 only contains bank 0 . Normally the register is set to Bright White0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models).The register can be used to select between the following eight predefined configurations only:  -Address- 0 1 2 3 4 5 6 7 0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0 4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7''' 8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2 C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3 The Video RAM is always located in the first 64K, VRAM is in no way affected by this register. == Programming the Gate Array - Examples ==

Defining the colours, <prebr>Setting pen 0 to Bright White. <pre>LD BC,7F00 &nbsp;;Gate Array portLD A,%00000000+0 &nbsp;;Pen number (and Gate Array function)OUT (C),A &nbsp;;Send pen numberLD A,%01000000+11 &nbsp;;Pen colour (and Gate Array function)OUT (C),A &nbsp;;Send it

Setting the mode and rom ROM configuration, Mode 2, upper and lower rom ROM disabled.

LD BC,7F00 &nbsp;;Gate array portLD A,%10000000+%00001110 &nbsp;;Mode and rom ROM selection (and Gate Array function)OUT (C),A &nbsp;;Send it

==== Conversion chart =Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

===== Note =====

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to it's its original colour. This is due to the firmware re- setting resetting the colour. When using the firmware, use it's its routines to select the colour, and the colour will remain.

{|{{Prettytable|widthExample: 700px[For whatever reason, this example does NOT refer to the above firmware stuff]<pre>ld bc,7f00+1&nbsp; font-size: 2em;}}Gate array function (set pen)|''Firmware ;and pen numberout (c),cld bc,7f00&nbsp;;41 ;Gate array function (set colour);and colour numberout (c),cret</pre> == Palette R,G,B definitions == There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.  To display a CPC image you will need to use a analogue monitor with a composite sync.  === Palette sorted by Hardware Colour Number''Numbers === {||''Colour Name''||''Hardware Number''||''Quick reference colour value'' class="FCK__ShowTableBorders"

|0''Hardware Number||BlackFirmware Number||20''Colour Name'' |''R&nbsp;%'' || ''G&54nbsp;%'' || ''B&nbsp;%'' || ''Colour''

|1 0 (40h) ||Blue13 ||4White ||&4450|| 50|| 50|| bgcolor="#808080" |

|2 1 (41h) ||Bright Blue(13) ||21White ||&5550|| 50|| 50|| bgcolor="#808080" |

|3 2 (42h) ||Red19 ||28Sea Green ||&5C 0||100|| 50|| bgcolor="#00ff80" |

|4 3 (43h) ||Magenta25 ||24Pastel Yellow ||&58100||100|| 50|| bgcolor="#ffff80" |

|5 4 (44h) ||Mauve1 || 29Blue ||&5D 0|| 0|| 50|| bgcolor="#000080" |

|6 5 (45h) ||Bright Red7 ||12Purple || &4C100|| 0|| 50|| bgcolor="#ff0080" |

|7 6 (46h) ||Purple10 || 5Cyan ||&45 0|| 50|| 50|| bgcolor="#008080" |

|8 7 (47h) ||Bright Magenta16 ||13Pink ||&4D100|| 50|| 50|| bgcolor="#ff8080" |

|9 8 (48h) ||Green(7) ||22Purple ||&56100|| 0|| 50|| bgcolor="#ff0080" |

|10 9 (49h) ||Cyan(25) ||6Pastel Yellow ||&46100||100|| 50|| bgcolor="#ffff80" |

|1110 (4Ah) ||Sky Blue24 ||23Bright Yellow ||&57100||100|| 0|| bgcolor="#ffff00" |

|1211 (4Bh) ||Yellow26 ||30Bright White ||&5E100||100||100|| bgcolor="#ffffff" |

|1312 (4Ch) ||White6 ||Bright Red ||100|| 0||&40 0|| bgcolor="#ff0000" |

|1413 (4Dh) ||Pastel Blue8 ||31Bright Magenta||&5F100|| 0||100|| bgcolor="#ff00ff" |

| 14 (4Eh) ||15 ||Orange ||14100|| 50|| 0||bgcolor="#ff8000" |&4E

|1615 (4Fh) ||Pink17 ||7Pastel Magenta||&47100|| 50||100|| bgcolor="#ff80ff" |

|1716 (50h) ||Pastel Magenta(1) ||15Blue ||&4F 0|| 0|| 50|| bgcolor="#000080" |

|1817 (51h) ||Bright (19) || Sea Green || 0||100||50|18|bgcolor="#00ff80" |&52

|1918 (52h) ||Sea 18 || Bright Green || 0||100|| 0|2|bgcolor="#00ff00" |&42

| 19 (53h) ||20 ||Bright Cyan ||19 0||100||100||bgcolor="#00ffff" |&53

|2120 (54h) ||Lime0 ||26Black ||&5A 0|| 0|| 0|| bgcolor="#000000" |

|2221 (55h) ||Pastel Green2 ||25Bright Blue ||&59 0|| 0||100|| bgcolor="#0000ff" |

|2322 (56h) ||Pastel Cyan9 ||27Green ||&5B 0|| 50|| 0|| bgcolor="#008000" |

|2423 (57h) ||Bright Yellow11 ||10Sky Blue ||&4A 0|| 50||100|| bgcolor="#0080ff" |

|2524 (58h) ||Pastel Yellow4 ||3Magenta ||&4350|| 0|| 50|| bgcolor="#800080" |

|2625 (59h) ||Bright White22 ||11Pastel Green ||&4B50||100|| 50|| bgcolor="#80ff80" |

Example: <pre>ld bc,7f00+1 ;Gate array function (set pen);and pen numberout (c),cld bc,7f00 ;41 ;Gate array function (set colour);and colour numberout (c),cret</pre> ==== Pallette R,G,B definitions ==== There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour. To display a CPC image you will need to use a analogue monitor with a composite sync. This table shows the relationship between hardware colour number, colour name and RGB mixing. Hardware Colour Index Colour Name RGB R % G % B %0 White 50 50 50 <br>1 White 50 50 50 <br>2 Sea Green 0 100 50 <br>3 Pastel Yellow 100 100 50 <br>4 Blue 0 0 50 <br>5 Purple 100 0 50 <br>6 Cyan 0 50 50 <br>7 Pink 100 50 50 <br>8 Purple 100 0 50 <br>9 Pastel Yellow 100 100 50 <br>10 Bright Yellow 100 100 0 <br>11 Bright White 100 100 100 <br>12 Bright Red 100 0 0 <br>13 Bright Magenta 100 0 100 <br>14 Orange 100 50 0 <br>15 Pastel Magenta 100 50 100 <br>16 Blue 0 0 50 <br>17 Sea Green 0 100 50 <br>18 Bright Green 0 100 0 <br>19 Bright Cyan 0 100 100 <br>20 Black 0 0 0 <br>21 Bright Blue 0 0 100 <br>22 Green 0 50 0 <br>23 Sky Blue 0 50 100 <br>24 Magenta 50 0 50 <br>25 Pastel Green 50 100 50 <br>26 Lime 50 100 0 <br>27 Pastel Cyan 50 100 100 <br>28 Red 50 0 0 <br>29 Mauve 50 0 100 <br>30 Yellow 50 50 0 <br>31 Pastel Blue 50 50 100 ==== RGB assignments for the software colours ==== This is simply a sidenote to illustrate a pattern in the RGB assignments of the software colours and to show how their value is calculated. {|{{Prettytable|width: 700px; font-size: 2em;}}|''Firmware Colour Number''||''Colour Name''||''R %''||''G %''||''B %'' class="FCK__ShowTableBorders"

|0''Firmware Number'' ||Black''Hardware Number'' ||0''Colour Name'' |''R&nbsp;%'' |0|''G&nbsp;%'' |0| ''B&nbsp;%'' || ''Colour''

|10||Blue54h ||Black || 0|| 0||50 0||bgcolor="#000000"|

|21|| 44h (or 50h) ||Bright Blue || 0|| 0||10050||bgcolor="#000080"|

|32||Red55h ||50Bright Blue || 0|| 0||100||bgcolor="#0000ff"|

|43||Magenta5Ch ||Red ||50|| 0||50 0||bgcolor="#800000"|

|54||Mauve58h ||Magenta ||50|| 0||10050||bgcolor="#800080"|

|65||Bright Red5Dh ||100Mauve ||050|| 0||100||bgcolor="#8000ff"|

|76||Purple4Ch ||Bright Red ||100|| 0||50 0||bgcolor="#ff0000"|

|87||Bright Magenta45h (or 48h) ||Purple ||100|| 0||10050||bgcolor="#ff0080"|

|98||Green4Dh ||0Bright Magenta ||50100|| 0||100||bgcolor="#ff00ff"|

|109||Cyan56h ||Green || 0||50||50 0||bgcolor="#008000"|

|1110||Sky Blue46h ||Cyan || 0||50||10050||bgcolor="#008080"|

|1211||Yellow57h ||50Sky Blue || 0||50||0100||bgcolor="#0080ff"|

|1312||White5Eh ||50Yellow ||50||50|| 0||bgcolor="#808000"|

|1413||Pastel Blue40h (or 41h) ||White ||50||50||10050||bgcolor="#808080"|

|1514||Orange5Fh ||100Pastel Blue ||50||050||100||bgcolor="#8080ff"|

|1615||Pink4Eh ||Orange ||100||50||50 0||bgcolor="#ff8000"|

|1716||Pastel Magenta47h ||Pink ||100||50||10050||bgcolor="#ff8080"|

|1817||Bright Green4Fh ||0Pastel Magenta ||100||050||100||bgcolor="#ff80ff"|

|1918||Sea 52h ||Bright Green || 0||100||50 0||bgcolor="#00ff00"|

|2019||Bright Cyan42h (or 51h) ||Sea Green || 0||100||10050||bgcolor="#00ff80"|

|2120||Lime53h ||50Bright Cyan || 0||100||0100||bgcolor="#00ffff"|

|2221||Pastel Green5Ah ||Lime ||50||100||50 0||bgcolor="#80ff00"|

|2322|| 59h ||Pastel CyanGreen ||50||100||10050||bgcolor="#80ff80"|

|2423||Bright Yellow5Bh ||Pastel Cyan || 50||100||100||0bgcolor="#80ffff"|

|2524||Pastel 4Ah ||Bright Yellow ||100||100||50 0||bgcolor="#ffff00"|

|2625||Bright White43h (or 49h) ||100Pastel Yellow ||100||100|| 50||bgcolor="#ffff80"|

=== Intensities === The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).* [[CPC Palette]] - some more details === To calculate the colour value: <br>=== '''Red'''  0% =&gt; do not add anything <br> 50% =&gt; add 3 <br> 100% =&gt; add 6 <br> '''Green <br>'''  0% =&gt; do not add anything <br> 50% =&gt; add 9 <br> 100% =&gt; add 18 <br> '''Blue <br>'''  0% =&gt; do not add anything <br> 50% =&gt; add 1 <br> 100% =&gt; add 2 === Green Screen Colours === On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information) == Pictures == <gallery>Image:40010_am2_metal.jpg|40010 GA Metal LayerImage:40010_am2_acid.jpg|40010 GA with Metal Layer removedImage:40226_am4_metal.jpg|40226 PreASIC Metal Layer</gallery> ==See also== *[[Gate Array and ASIC Pin-Outs]] *[[Video modes]] : for other informations on colours and pixels. *[[CRTC]] : the other video stuff.*[[ASIC]] : for Plus users *[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC. * [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Gate Array schematics - reverse engineered by Gerald]

Green Screen Colours== External links ==On a green screen (where all colours are shades of green), the colours (in the software* [https:/firmware colours), are in order of increasing intensity/www. So that black is very dark, and white is bright green, and colour 13 is a medium greengrimware. org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (Thanks to Mark Rison for this informationin french) <br>]

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