Changes
8255
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== Port Usage ==
Bit 7 SF Must be "0" in this case
[[File:Intel 8255A - BSR control word format8255 Control0.jpgpng]]
=== PPI Control with Bit7=1 ===
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.
[[File:Intel 8255A - IO modes control word format8255 Control1.jpgpng]]
== Group Modes ==
In some of these modes , port C is used as a control/status port for port A or B. It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the user to set or reset any individual bits in port C.
=== Mode 0 – Simple Input/output mode ===
In this mode , the 8 bit port A (PA0-PA7) of 8255 IC ports can be configured as input or output portused for simple I/O operations without handshaking signals. In the similar fashion Port A, port B (PB0-PB7) can also configured as input or output provide simple I/O operation. However there is flexibility for the The two halves of port C. It can be divided into two either used together as an additional 8-bit port, or they can be used as individual 4 -bit ports, . Since the two halves of port CLower (PC0-PC3) and port CUpper (PC4-PC7). Each of them can set independently for input or output operation. In this way we can say there C are four ports (port-Aindependent, portthey may be used such that one-B, port CLower and port CUpper) and each of them can set either half is initialized as an input port or while the other half is initialized as an output port. Here these ports are simple input or output ports. That means these ports can work without handshaking. In this mode the outputs are latched whereas the inputs are not latched.
[[File:8255 - mode-0.png]]
[[File:8255 - mode-2.png]]
=== Port pins summary ===
[[File:8255 - Port pins.gif]]
== Programming Examples ==
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= Block Diagram = [[File:Block-diagram-of-8255-lBlock Diagram.jpgpng]] = Amstrad ASIC PPI = *The 8255 PPI is not emulated by the Pre-ASIC. These CPC’s have a real PPI chip and therefore behave like the first generation of CPC’s.*The ASIC PPI does not support Group Modes other than Groupe Mode 0.*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports.
= Resources =
* [[Media:Intel_8255A_DatasheetIntel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PIO]]PPI
= Links =
