Changes
8255
, Bit 7 SF Must be "0" in this case
[[File:Intel 8255A - BSR control word format8255 Control0.jpgpng]]
=== PPI Control with Bit7=1 ===
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.
[[File:Intel 8255A - IO modes control word format8255 Control1.jpgpng]]
== Group Modes ==
</pre>
= Block Diagram = [[File:Block-diagram-of-8255-lBlock Diagram.jpgpng]] = Amstrad ASIC PPI = *The 8255 PPI is not emulated by the Pre-ASIC. These CPC’s have a real PPI chip and therefore behave like the first generation of CPC’s.*The ASIC PPI does not support Group Modes other than Groupe Mode 0.*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports.
= Resources =
* [[Media:Intel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PIO]]PPI
= Links =
