Changes
8255
,== 8255 Part numbers used in the CPC during its lifetime ==
* NEC D8255AC-2
* NEC D8255AC-5
* Toshiba TMP8255AP-5
All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.
== The 8255 in the CPC ==
The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe it's its role in the Amstrad CPC,CPC+ and KC compact systems. To understand it's its full functions please read the datasheet.
In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.
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== Port Usage ==
|6||PRN.BUSY||Parallel/Printer port ready signal, "1" = not ready, "0" = Ready||Same as on CPC
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|5||/EXP||Expansion Port /EXP pin||Printer data bit7Same as on CPC
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|4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Purpose unknown (not same as on CPC?) (set Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
|-
|3||LK3||Manufacturer rowspan="3" |3bit Distributor ID bit3. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
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|2||LK2||Manufacturer ID bit2||Purpose unknown (set to "0")
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|1||LK1||Manufacturer ID bit1||Expansion Port /TEST pin
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|0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
* LK1-4 are links on the mainboard ("0" bits are wired to GND). On CPC464,CPC664,CPC6128 and GX4000 they are labeled LK1-LK4, on the CPC464+ and CPC6128+ they are labeled LK101-LK103 (and LK104, presumably?).
* Bit5 bit is connected to (/EXP signal on the expansion port.** On the KC Compact this bit is used to define bit 7 of the printer data (see [[8bit Printer Ports]]).** On the CPC, it is possible to use this bit to define bit 7 of the printer data, so a 8-bit printer port is made, with a hardware modification,** On the CPC this can be used by a expansion device to report it's its presence. "1" = device connected, "0" = device not connected. This is not always used by all expansion devices. ''is it used by any expansions?''[in the DDI-1 disc interface, /EXP connects to the ROM bank selection, bank 0 or bank 7]
== PPI Port C ==
|6||PSG BC1||
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|5||Cassette Write data||Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])
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|4||Cassette Motor Control||set bit to "1" for motor on, or "0" for motor off
== PPI Control ==
This register has two different functions depending on bit7 of the data written to this register. === PPI Control with Bit7=0 ===If Bit 7 is "0" then the register is used to set or clear a single bit in Port C: Bit 0 B New value for the specified bit (0=Clear, 1=Set) Bit 1-3 N0,N1,N2 Specifies the number of a bit (0-7) in Port C Bit 4-6 - Not Used Bit 7 SF Must be "0" in this case [[File:8255 Control0.png]] === PPI Control with Bit7=1 ===Otherwise, if Bit 7 is "1" then the other bits will initialize Port Group Modes and Ports A-B -Cupper-Clower as Input or Output:
Bit 0 IO-Cl Direction for Port C, lower bits (always 0=Output in CPC)
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.
== Programming Examples ==
LD E,&FF ;Data to put into port
OUT (C),A E ;Send to port A
;Return port I/O status and operating modes
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= Block Diagram = [[ImageFile:8255 ppi 1Block Diagram.jpgpng]] = Amstrad ASIC PPI = *The 8255 PPI is not emulated by the Pre-ASIC. These CPC’s have a real PPI chip and therefore behave like the first generation of CPC’s.*The ASIC PPI does not support Group Modes other than Groupe Mode 0.*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports.
= Resources =
* [[Media:Datasheet of the 8255Intel8255A_datasheet.pdf]]PPI Datasheet (Intel)* [[VHDL Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)* [https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PIO]]PPI
= Links =
*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)] [[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]