Changes

Bit 0 of the vector will be 0. Bits 32..1 are generated by the ASIC based on the interrupt source (one of the DMA channels or raster interrupt). Bits 7..4 3 are defined by writing a value to the ASIC IVR register (at &6805 in the ASIC registers).

The This bug relates to has mostly been seen when using the raster interrupt. When a raster interrupt is acknowledged sometimes the vector will be 6 (for raster interrupt) or 4 (for dma channel 0 - the lowest priority interrupt).

For example, if DMA interrupts are not used and when a raster interrupt is acknowledged sometimes the vector will be 6 (for raster interrupt) or 4 (for dma channel 0 - the lowest priority interrupt). * If the instruction at the time of interrupt acknowledge is located in a memory region where A13=0 then the bug happens. The bug is not dependent on RAM or ROM or I register value. The location of the interrupt handler code is also not important. The location of the instruction is important. The bug also doesn't occur with opcodes that don't use memory read/write or don't contain a memory read/write when fetching the opcode. Single byte instructions are fine including HALT. However, it is difficult to code in a way to workaround the issue in this way.