Following discussions on cpcwiki involving roudoudou, Longshot, gerald, arnoldemu and dragon the cause of the bug has been identified, through testing and from analysis by gerald with his logic analyzer and a workaround has been identified.
The This bug relates to has mostly been seen when using the raster interrupt. When For example, if DMA interrupts are not used and when a raster interrupt is acknowledged sometimes the vector will be 6 (for raster interrupt) or 4 (for dma channel 0 - the lowest priority interrupt).
* If the instruction at the time of interrupt acknowledge is located in a memory region where A13=0 then the bug happens. The bug is not dependent on RAM or ROM or I register value. The location of the interrupt handler code is also not important. The location of the instruction is important. The bug also doesn't occur with opcodes that don't use memory read/write or don't contain a memory read/write when fetching the opcode. Single byte instructions are fine including HALT. However, it is difficult to code in a way to workaround the issue in this way.
* If the instruction at the time of interrupt acknowledge is located in a memory region where A13=1 then the bug doesn't happen.
* If auto-clear DMA interrupts are enabled (IVR bit 0=0), then the bug can also happen with the DMA interrupts.
There are workarounds:
The logic around the Z80 shortens or lengthens the IORQ based on A13 and that is why the bug doesn't happen when A13=1.
== Weblinks ==
*[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/amstrad-plus-and-im2-bug/ Amstrad Plus and IM2 bug] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/asic-im-2-vector/ ASIC IM2 vector] Related topics on CPCWiki forum
*[https://asmtradcpc.zilog.fr/docs/Interruptions_-_modes_et_fonctionnement.php Le bug des interruptions cpc+ (FR)]
*[http://quasar.cpcscene.net/doku.php?id=assem:asic#les_interruptions_de_l_asic Le bug DMA0 vs PRI (FR)]
[[Category:Hardware]]