Changes
CRTC
,/* CRTC Type Detection */
The '''CRTC''' (Cathode Ray Tube Controller) generates helps to generate the video signal of the Amstrad CPC. NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
== Overview ==
The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.
The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Part number''||''Manufacturer''||''Type number(note 3)''|-|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|AMS40489||Amstrad||3 (note 1)
|-
|???40226||Amstrad?||4 (note 2)
|}
1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.
2. As far as I know, this This type exists only in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" CPC6128, the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.
3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.
It is possible to detect the 6845 present using software methods, and this is done to:
* warn that the software was not designed for the detected 6845 and may function incorrectly, * to adapt the software so that it will run with the detected 6845 * In most cases, the type of the detected 6845 is reported.
4. As far as I know, the KC compact used HD6845R only.
==Programming== The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system. The recommended I/O port addressess addresses are
{|{{Prettytable|width: 700px; font-size: 2em;}}
'''NOTE'''
1. The function of these I/O ports is dependant on the CRTC type Signals 2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus. ==Addressing==
The following table defines the generated memory address from the CRTC and Gate-Array signals.
|''Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA12 MA13
|-
|A14||6845||MA11 MA12
|-
|A13||6845||RA2
|}
CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.
== DISPTMG ==
DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2. The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
== HSYNC and VSYNC ==
On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array. The When HSYNC is active Gate-Array modifies outputs the signals and palette colour black. If the HSYNC is set to 14 characters then mixes these black will be output for 14us. The HSYNC is modified before being sent to form the Composite-Sync which monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51. On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array. The VSYNC is also modified before being sent to the display monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width. Using CRTC1, VSYNC width value 0 means a value of 16. == The 6845 DesignRegisters==
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total(-1)||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total(-1)||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed ||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync position Position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew ||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address (aka Scan Line) (-1)||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster ||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster ||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High) ||xx000000||48
|-
|13||Display Start Address (Low) ||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High) ||xx000000||0
|-
|15||Cursor Address (HighLow) ||00000000||0
|-
|16||Light Pen Address (High) ||xx000000||||Read Only
|-
|17||Light Pen Address (HighLow) ||00000000||||Read Only
|-
|}
registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.
Details about Reg. 12 and Reg. 13 specifically:
.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'
So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
== CRTC Differences ==
{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=43|''Type''
|-
|0||1||& 2||3 & 4
|-
|0||Horizontal Total(-1)||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|1||Horizontal Displayed||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|2||Horizontal Sync Position||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|3||Horizontal and Vertical Sync Widths||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|4||Vertical Total(-1)||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|5||Vertical Total Adjust||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|6||Vertical Displayed||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|7||Vertical Sync positionPosition||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|8||Interlace and Skew||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|9||Maximum Raster Address(aka Scan Line) (-1)||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Read Only||(note 2)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Read Only||(note 2)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)
|-
|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write|colspan=3 style="text-align: center;"|Read/Write (note 2) ***check
|-
|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write|colspan=3 style="text-align: center;"|Read/Write (note 2) **check
|-
|16||Light Pen Address (High)||Read Only||Read Only||Read Only|colspan=3 style="text-align: center;"|Read Only (note 2) **check
|-
|17||Light Pen Address (HighLow)||Read Only|colspan=3 style="text-align: center;"|Read Only||Read Only||Read Only (note 2) **check
|-
|}
'''Notes'''
== Links ==
* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]* [https://cpcrulez.fr/coding_CRTC-Paradox.htm Dossier CRTC (Gozeur/Paradox)]* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]* [[Media:ACCC1.7-EN.pdf]] [[Media:ACCC1.7-FR.pdf]] CPC CRTC Compendium - Latest (10/2023!) document containing in-depth info about CRTC programming on CPC. ==Related pages== *[[Gate Array]] *[[ASIC]] *[[Video modes]] *[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.
[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Programming]] [[Category:StubDatasheet]] [[Category:Graphic]]