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Gate Array
In the [[KC compact]] CPC+ system, the functions of the Gate-Array are "emulated" in integrated into a single [[TTL logicASIC|ASIC]] . When the ASIC is "locked", the extra features are not available and by the [[Zilog Z8536 CIO]]ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
In the "cost-down" version of the CPC6128[[KC Compact]] system, the functions of the Gate-Array are integrated into a ASIC"emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
The recommended gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is &7Fxxset to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".
The recommended I/O port address is &7Fxx. The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|0''Data Bit 7''||0''Data Bit 6''||Select pen''Function''
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|0||10 ||Select colour for selected pen
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|10 ||01 ||Select screen mode, rom configuration and interrupt controlcolour for selected pen
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| 1 || 0 || Select screen mode, ROM configuration and interrupt control|-|1||1||Ram RAM Memory Management (note 1)
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===== Note ===== This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464,CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K Ram Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a PAL located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on Ram Management for more information.
=== Summary ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|7''Bit'' ||0''Value'' ||Gate Array function "Pen Selection"''Function''
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|67 ||0||rowspan="2" | Gate Array function "Pen Selection"
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|56 ||x||not used0
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|45 ||1- ||Select bordernot used
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|34 ||x1 ||ignoredSelect border
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|23 ||x||ignoredrowspan="4" | Ignored
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|12 ||x||ignored
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|01 ||x||ignored
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| 0 || x
|}
<br>
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|7''Bit'' ||0''Value'' ||Gate Array function "Pen Selection"''Function''
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|67 ||0||rowspan="2" | Gate Array function "Pen Selection"
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|56 ||x||not used0
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|45 ||1- ||Select pennot used
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|34 ||x0 ||Pen numberSelect pen
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|23 ||x||rowspan="4" | Pen number
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|12 ||x||
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|01 ||x||
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| 0 || x
|}
==== Register 1 - Palette Data (Colour selection ==) ==
Once the pen has been selected the its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.
Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|7''Bit'' ||0''Value'' ||Gate Array function "Colour selection"''Function''
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|67 ||10 ||rowspan="2" | Gate Array function "Colour selection"
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|56 ||x||not used1
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|45 ||x- ||Colour number xnot used
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|34 ||x||rowspan="5" | Colour number x
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|23 ||x||
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|12 ||x||
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|01 ||x||
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| 0 || x
|}
==Register 2 - Select screen mode and ROM configuration == Hardware colour palette This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration. ===Screen mode selection === The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|''Bit 1'' || ''Bit 0'' ||White''Screen mode''
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|10 ||White (note 1)0 || Mode 0, 160x200 resolution, 16 colours
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|20 ||Sea Green1 || Mode 1, 320x200 resolution, 4 colours
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|31 ||Pastel Yellow0 || Mode 2, 640x200 resolution, 2 colours
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|1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)|} * Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3). Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC. === ROM configuration selection === Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM. Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM. Bit 4controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information. === Summary === {|{{Prettytable|Bluewidth: 700px; font-size: 2em;}}
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|5''Bit'' ||Purple''Value'' || ''Function''
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|67 ||Cyan1 || rowspan="2" | Gate Array function
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|76 ||Pink0
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|85 ||Purple (note 1)- || not used
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|94 ||Pastel Yellow (note 1)x || Interrupt generation control
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|103 ||Bright Yellowx || 1=Upper ROM area disable, 0=Upper ROM area enable
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|112 ||Bright Whitex || 1=Lower ROM area disable, 0=Lower ROM area enable
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|121 ||Bright Redx || rowspan="2" | Screen Mode slection
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|130 ||Bright Magentax|-}|14||Orange|== Register 3 -RAM Banking ==|15||Pastel Magenta|-|16||Blue This register exists only in CPCs with 128K RAM (note 1like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|-PAL]] that assists the Gate Array chip.|17||Sea Green (note 1){|-|18||Bright Green{{Prettytable|width: 700px; font-|19||Bright Cyan|-|20||Black|-|21||Bright Bluesize: 2em;}}
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|22''Bit'' ||Green''Value'' || ''Function''
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|237 ||Sky Blue1 || rowspan="2" | Gate Array function 3
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|246 ||Magenta1
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|255 ||Pastel Greenb || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
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|264 ||Limeb
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|273 ||Pastel Cyanb
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|282 ||Redx || rowspan="3" | RAM Config (0..7)
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|291 ||Mauve|-|30||Yellow|-|31||Pastel Bluex
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| 0 || x
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==== Screen mode selection ==Programming the Gate Array - Examples ==
===== Summary ===Palette R,G,B definitions ==
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|7''Hardware Number||0Firmware Number||Gate Array function ''Colour Name'' | ''R %'' || ''G %'' || ''B %'' || ''Colour''
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|6 0 (40h) ||113 || White || 50|| 50|| 50|| bgcolor="#808080" |
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|5 1 (41h) ||x(13) ||not usedWhite || 50|| 50|| 50|| bgcolor="#808080" |
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|4 2 (42h) ||x19 ||Interrupt generation controlSea Green || 0||100|| 50|| bgcolor="#00ff80" |
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| 3(43h) ||x25 ||*1 Upper rom area disable*0 Upper rom area enablePastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
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|2 4 (44h) ||x1 ||*1 Lower rom area disable*Blue || 0 Lower rom area enable|| 0|| 50|| bgcolor="#000080" |
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|1 5 (45h) ||x7 ||Mode slectionPurple ||100|| 0|| 50|| bgcolor="#ff0080" |
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| 6 (46h) || 10 || Cyan || 0||x50|| 50||bgcolor="#008080" |
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| 7 (47h) || 16 || Pink ||100|| 50|| 50|| bgcolor="#ff8080" |
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| 8 (48h) || (7) || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
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| 9 (49h) || (25) || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
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| 10 (4Ah) || 24 || Bright Yellow ||100||100|| 0|| bgcolor="#ffff00" |
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| 11 (4Bh) || 26 || Bright White ||100||100||100|| bgcolor="#ffffff" |
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| 12 (4Ch) || 6 || Bright Red ||100|| 0|| 0|| bgcolor="#ff0000" |
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| 13 (4Dh) || 8 || Bright Magenta||100|| 0||100|| bgcolor="#ff00ff" |
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| 14 (4Eh) || 15 || Orange ||100|| 50|| 0|| bgcolor="#ff8000" |
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| 15 (4Fh) || 17 || Pastel Magenta||100|| 50||100|| bgcolor="#ff80ff" |
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| 16 (50h) || (1) || Blue || 0|| 0|| 50|| bgcolor="#000080" |
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| 17 (51h) || (19) || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
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| 18 (52h) || 18 || Bright Green || 0||100|| 0|| bgcolor="#00ff00" |
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| 19 (53h) || 20 || Bright Cyan || 0||100||100|| bgcolor="#00ffff" |
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| 20 (54h) || 0 || Black || 0|| 0|| 0|| bgcolor="#000000" |
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| 21 (55h) || 2 || Bright Blue || 0|| 0||100|| bgcolor="#0000ff" |
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| 22 (56h) || 9 || Green || 0|| 50|| 0|| bgcolor="#008000" |
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| 23 (57h) || 11 || Sky Blue || 0|| 50||100|| bgcolor="#0080ff" |
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| 24 (58h) || 4 || Magenta || 50|| 0|| 50|| bgcolor="#800080" |
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| 25 (59h) || 22 || Pastel Green || 50||100|| 50|| bgcolor="#80ff80" |
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| 26 (5Ah) || 21 || Lime || 50||100|| 0|| bgcolor="#80ff00" |
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| 27 (5Bh) || 23 || Pastel Cyan || 50||100||100|| bgcolor="#80ffff" |
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| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" |
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| 29 (5Dh) || 5 || Mauve || 50|| 0||100|| bgcolor="#8000ff" |
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| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| bgcolor="#808000" |
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| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| bgcolor="#8080ff" |
|}
== Programming the Gate Array - Examples = Palette sorted by Firmware Colour Numbers ===
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|0''Firmware Number'' ||Black''Hardware Number'' ||20''Colour Name'' |''R %'' || ''G&54nbsp;%'' || ''B %'' || ''Colour''
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|10||Blue54h ||4Black ||&44 0|| 0|| 0||bgcolor="#000000"|
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|21|| 44h (or 50h) ||Bright Blue || 0|| 0||50|21|bgcolor="#000080"|&55
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|32||Red55h ||28Bright Blue ||&5C 0|| 0||100||bgcolor="#0000ff"|
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|43||Magenta5Ch ||24Red ||&5850|| 0|| 0||bgcolor="#800000"|
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|54||Mauve58h || 29Magenta ||&5D50|| 0|| 50||bgcolor="#800080"|
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|65||Bright Red5Dh ||12Mauve || &4C50|| 0||100||bgcolor="#8000ff"|
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|76||Purple4Ch || 5Bright Red ||&45100|| 0|| 0||bgcolor="#ff0000"|
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|87||Bright Magenta45h (or 48h) ||13Purple ||&4D100|| 0|| 50||bgcolor="#ff0080"|
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|98||Green4Dh ||22Bright Magenta ||&56100|| 0||100||bgcolor="#ff00ff"|
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|109||Cyan56h ||6Green ||&46 0|| 50|| 0||bgcolor="#008000"|
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|1110||Sky Blue46h ||23Cyan ||&57 0|| 50|| 50||bgcolor="#008080"|
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|1211||Yellow57h ||30Sky Blue ||&5E 0|| 50||100||bgcolor="#0080ff"|
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|1312||White5Eh ||Yellow || 50|| 50|| 0||&40bgcolor="#808000"|
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|1413||Pastel Blue40h (or 41h) ||31White ||&5F50|| 50|| 50||bgcolor="#808080"|
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|1514||Orange5Fh ||14Pastel Blue || 50|| 50||100||bgcolor="#8080ff"|&4E
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|1615||Pink4Eh ||7Orange ||&47100|| 50|| 0||bgcolor="#ff8000"|
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|1716||Pastel Magenta47h ||15Pink ||&4F100|| 50|| 50||bgcolor="#ff8080"|
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|1817||Bright Green4Fh ||18Pastel Magenta ||&52100|| 50||100||bgcolor="#ff80ff"|
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|1918||Sea 52h ||Bright Green || 0||100|| 0|2|bgcolor="#00ff00"|&42
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|2019||Bright Cyan42h (or 51h) ||19Sea Green || 0||100|| 50||bgcolor="#00ff80"|&53
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|2120||Lime53h ||26Bright Cyan ||&5A 0||100||100||bgcolor="#00ffff"|
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|2221||Pastel Green5Ah ||25Lime ||&5950||100|| 0||bgcolor="#80ff00"|
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|2322|| 59h ||Pastel CyanGreen || 50||100||50|27|bgcolor="#80ff80"|&5B
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|2423||Bright Yellow5Bh ||10Pastel Cyan ||&4A50||100||100||bgcolor="#80ffff"|
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|2524||Pastel 4Ah ||Bright Yellow ||100||100|| 0|3|bgcolor="#ffff00"|&43
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|2625||Bright White43h (or 49h) ||11Pastel Yellow ||&4B100||100|| 50||bgcolor="#ffff80"|
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|26|| 4Bh ||Bright White ||100||100||100||bgcolor="#ffffff"|
|}
==== Pallette R,G,B definitions ==Pictures ==
*[[CRTC]] : the other video stuff.
*[[ASIC]] : for Plus users
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]
