Changes
/* External links */
== Register 3 - RAM Banking ==
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL ]] that assists the Gate Array chip.
{|{{Prettytable|width: 700px; font-size: 2em;}}
-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4 ''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0 4000-7FFF RAM_1 RAM_1 '''RAM_5 ''' '''RAM_3 ''' '''RAM_4 ''' '''RAM_5 ''' '''RAM_6 ''' '''RAM_7''' 8000-BFFF RAM_2 RAM_2 '''RAM_6 ''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2 C000-FFFF RAM_3 '''RAM_7 ''' '''RAM_7 ''' '''RAM_7 ''' RAM_3 RAM_3 RAM_3 RAM_3
The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
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