Sixteen hardware sprites are to be provided by the ASIC.
Each consists of an array of 16x16 pixels of four bits per pixel. A sprite pixel is "transparent" when it has a value of zero, thus allowing 15 sprite colours. The sprite pixel data exists in memory mapped registers with the ASIC, from address 4000h. The lower four bits of each byte contain the data for a single pixel. The first 16 bytes contain the data for the upper scan line, starting at the top left hand corner of the sprite. 15 more similar scan lines of 16 pixels each follow, thus each 256 (0100h) byte block of register space contains one sprite. When the pixel data for a sprite is read or written, that sprite is removed from the display for the duration of the access. Thus sprite pixel data should only be accessed during retraced time, or while the raster is scanning somewhere else, otherwise there is a risk of disruption of the displayto avoid this.
The position on screen of the upper left corner of each sprite, and the X and Y magnification, are defined by five registers for each sprite:
All sprite characteristics are independent of the main screen mode, the unmagnified pixel size being as for screen mode 2 (640x200). Sprite colours are defined by 15 entries in the colour palette (see section 2.2 below). Thus sprites can be in different colours and resolutions from the rest of the screen. Sprites may overlay with each other or the border, and are prioritized so that the border has the highest priority, followed by sprites 0 to 15 in sequence, then the main screen data. Thus sprites always appear "in front of" the main screen and behind "the border".
When writing offsets +3,+4,+5 and +7 you can set the sprite magnification. +4 to +7 are mirrors.
When reading +3 and +4 you will read X position, +5 and +7 will read Y position. They are mirrors of X,Y values.
When the sprite pixel data is read or written, only the sprite whose pixels are being accessed is disabled (e.g. reading or writing in the range &4000-&40ff will only cause sprite 0 to be affected.). The pixels are not disrupted, the sprite will continue to be displayed after the read/write is done with no corruption to the image of the sprite. At the point the read/write is done, the sprite is disabled and what you will see behind is the pixels from a lower priority sprite or the background depending on what is behind. The read/write interrupts the display of the sprite at that moment. A write of 1us seems to only affect a width of 1 byte (i.e. 4 mode 1 pixels) rather than the full 1us time. Writing to the sprite X,Y or magnification doesn't cause the sprite to be disabled, but note writing a different X or Y coordinate will cause the sprite to be cut and appear at the new location when it's reached.
If you update a sprite which is covered by a lower priority sprite or the border then you will not see the effect.
===Colour palette===
10-1F border colour</pre>
NOTE: If you use a 16-bit write to write to the palette (e.g. LD HL,&0FFF: LD (&6400),HL then you will see the colour change as a result of first the low byte, then the high byte so that if you are writing black and then white, you will see another colour at the point of changing the colours. If you don't want to see this, then you can use the CPC OUT method but be restricted to the 27 CPC colours).
===Split Screen facility===
Three new memory mapped registers have been added within the ASIC, to provided provide a horizontally split screen facility. One at address 6801h defines the scan line after which the screen split occurs. A value of zero (as at power on reset) will turn this feature off.
The other register pair at 6802h and 6803h define the start address in memory to show for the split.
The screen can be split multiple times in a single frame by reprogramming 6801h, 6802 and 6803h.
The address takes the same form as R12 and R13 of the 6845 (e.g. &3000 being for the split to start at &c000). Any CRTC address can be used (the split may therefore scroll). 6802h is the high byte of the address and 6803h is the low byte of the address.
The full address that is displayed is defined by the soft scroll register, 6845's internal scan line counter and the programmed address.
The When VCC=R4 and RCC=R9 the programmed address is stored when 6845's Horizontal counter matches R0 on the line programmed, at other times the programmed address is stored when 6845's Horizontal counter matches Horizontal Displayed (R1) on the line programmed. It The value is then loaded into 6845never used when VCC=0 and RCC=0, R12/R13 are always used here so you can's MA counter t trigger the split to happen on the line after. Note that because scanline before a new frame and change the address is loaded into MA it effects of the rest first scanline of a frame. If you do the screen until value is used at the next time it is re-available line. (e.g. VCC=0, RCC=1). At all other times the programmed or split value is used to set MA on the display restartsnext scanline.
Note that because the address is loaded into MA it effects the rest of the screen until the next time it is re-programmed or the display restarts.
Note that care should be taken with programming this facility such that the screen split does not alter the function of address bits A1-A8 and the dynamic memory refresh is not upset. This can be accomplished by setting the start of the second screen to lie on 16k boundary. The reason is that the dynamic memory refresh is derived from the memory address that the 6845 describes.
The split line is 8-bit only and has a range of 0-255 and will wrap around (255->0). A normal screen has 312 scanlines. This means that with some values, the counter will wrap and the split line will occur 2 times. With a normal screen of 312 scan lines, the value 312 - 257 = 55, or 37h should not be programmed, otherwise instead of seeing a split at line 55, you see a split at line 2. To avoid this (1) the vertical total adjust register is set to 1 while 6801h contains 37h (or some other value where the wrap will occur before the new frame starts), or (2) the raster interrupt (see 2.4 below) should be used such that 6801h contains 0 during vertical retrace so that it is disabled and doesn't wrap.
EDIT: A programmed value of 1 shows 2 lines before the split.The value is captured when HCC=R1 on line 1, and used on the next line. A programmed value of 0 turns off the split. Therefore the only way to have a single line then have a split to happen on the 2nd line is to allow ensure the counter to wrap around wraps by setting the value to 55 (normal screen) as mentioned above. EDIT: Screen split can occur during the first char line of vertical adjust (i.e. R5>0 and RC<=8) but not at any other time. i.e. RC>8). If R5 is set to 31, you can split during the first 8 lines only.
===Programmable raster interrupt===
Setting the SSCR to zero, as at reset, (i.e. no offsets, no border), will of course effectively disable soft scroll.
== 6845's MA ==
NOTE: It seems the 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:
# When the split screen address is set, split screen line has been reached and Horizontal Counter equals Horizontal Displayed.
# When Raster Counter + Soft scroll matches R9 and Horizontal Counter equals Horizontal Displayed.
# When Vertical character count is reset to 0, it is then loaded from R12 and R13.
It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.
===Automatic feeding of sound generator===
The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.
The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. The loop counter is presumably not reset either when the channel is disabled (unconfirmed). Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).
The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.
* AY read/write operation
AY "inactive" state appears to be needed The exact timing is based on 1us cycles as follows. After the leading edge from HSYNC from the 6845 there is one dead cycle followed by an instruction fetch cycle for register selection onlyeach channel which is active (i. It doesn't appear to be needed e. enabled and not paused). The execute cycles then follow for each AY active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register read/write operation.
Example 1:
The exact timing is based on 1us cycles as follows. After the leading edge from HSYN from the 6845 there is one If DMA channel 0 and 2 are active: <dead cycle followed by an >, <instruction fetch cycle for each dma channel which is active (i.e. enabled and not paused). The 0>, <instruction fetch dma channel 2>, <instruction execute cycles then follow for each active dma channel. All instructions 0>,<instruction execute in one dma channel 2> Example 2: If DMA channel 2 is only active: <dead cycle>, except that LOAD requires at least 8 cycles. An extra cycle <instruction fetch dma channel 2>,<instruction execute dma channel 2> NOTE: DCSR is added to a LOAD if readable in the CPU is accessing the 8255range 6c00-6c0f, or two extra cycles if the CPU access was itself a PSG register writebut only appears to be writeable at 6c0f.
===Interrupt service (Vectored interrupts)===
</pre>
The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared. The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should therefore always set up the IVR before placing the CPU in vectored interrupt modeso that the top bit 5 bits are defined.
The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.
Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the DCSR are set if interrupts from sound channels 0-2 respectively are active. These bits can be ignored by software which uses vectored interrupts where the DMA interrupts are automatically cleared, or by software which does not use the DMA channel interrupt facility. If DMA channel interrupts are used and not automatically cleared, they must be acknowledged by writing a “1” to the relevant DCSR bit. If bit D0 of the IVR is set to 0 bits D4-D6 of the DCSR will be cleared before the CPU gets a chance to read them.
If IVR bit 0 is set to 1, a DMA channel is interrupting and is not acknowledged then it will continue to interrupt until it is acknowledged.
Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.Failure to observe this requirement may result in raster interrupts being missed.
Software which uses interrupts from expansion cards must always use Z80 non-vectored interrupt mode 1, because the expansion bus does not support vectored interrupts. (The ASIC doesn't recognise the RETI command sequence and the expansion bus doesn't support IEO or IEI which is used to control IM2 interrupt priority.)
To summarize, vectored software should place a valid vector (D0 = 0) into the IVR. The hardware will supply a different vector for each interrupt source, and all interrupts are acknowledge automatically.
Non vectored software must write a "1" to bit D0 of the IVR, or leave it in it's reset state. Interrupt service software must examine bit D7 of the DCSR first, followed by bits D4-D6 (in any sequence) to identify the interrupt source. DMA interrupts must be acknowledged by writing a "1" to the relevant DCSR bit.
Vectored interrupts are bugged. See [[Plus Vectored Interrupt Bug]] for more details.
===Enhanced ROM cartridge support===
The "write through" mechanism, whereby writes to an area which is currently mapped as ROM actually write to the underlying RAM, still functions, wherever the ROM is mapped. However the write through mechanism cannot be used to access the register page. Write through also does not operate to the RAM from the register page.
At reset, page 0 is visible in the range &0000-&3fff. DFxx is reset to 0 at this time(logical page is set to 0). This means on GX4000 page 1 will be visible at &c000-&ffff. On the Plus, it depends on /EXP. If /EXP is low, page 1 will be visible at &c000-&ffff, otherwise page 3 will be visible and CPM will be auto booted. On an unmodified GX4000, selecting logical page 7 using DFxx doesn't select physical page 3, instead it selects physical page 1. The appropiate hardware is not activated as it is on 464 and 6128.
===Analogue paddle ports===
Because of timescale pressures, the data separator design in the ASIC has been deleted rather than improved . Thus all models with a disk drive use an external SED9420 data separator.
=== 6845's MA ===
NOTE: The 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:
# When the split screen address is set, split screen line has been reached and Horizontal Counter equals Horizontal Displayed.
# When Raster Counter + Soft scroll matches R9 and Horizontal Counter equals Horizontal Displayed.
# When Vertical character count is reset to 0, it is then loaded from R12 and R13.
It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.
===8255===
* When switching port A of ASICs emulated 8255 to input, FF is present on the emulated 8255's port A outputs.
This will cause an invalid PSG register to be selected:
ld bc,&f400
out (c),c
ld bc,&f6c0
out (c),c
ld bc,&f792
out (c),c
;; At this point FF appears in emulated 8255 port A. This selects an invalid PSG register '&ff', when read &FF is returned. This is one source of keyboard reading bugs.
Therefore use this:
ld bc,&f400
out (c),c
ld bc,&f6c0
out (c),c
ld bc,&f600 ;;; << use inactive
out (c),c
ld bc,&f792
out (c),c
* When switching input/output of port A, on a normal 8255, the outputs are all cleared to 0. This doesn't happen on the emulated 8255. This is another source of keyboard reading bugs.
===Reading of write-only I/O registers===
There is no hardware that is driving these registers so the data is what is last on the z80 data bus.
NOTE: That because 7fxx is mapped to gate-array and both read/write can access it it is possible to read the colour register and display a raster on the screen. In this case the raster will use colours based on the last byte of the instruction.
===Reading of unmapped ASIC register RAM===
There is no hardware that is driving these registers so the data is what is last on the z80 data bus.
NOTE: Reading 6800-6806, which are mapped to write, also shows the same as unmapped addresses.
===Digital joysticks===
POR column indicates whether a register has power on reset. A "N" indicates that the contents of a register are undefined at power on.
At reset time, emulated PPI port A is set to input, port B is always input, port C is always output.
==APPENDIX II==