== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the Gate Array can only access the Base 64k page of RAM.
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== PAL I/O port ==
For RAM banking settings see Register 3 of the [[Gate Array]]. Note that no settings are stored in the Gate Arrayregarding register 3, but the PAL and Gate Array share an I/O port address.
Bit 14 Bit14 of the PAL selection address must can be at 0 or 1 on CPCs equipped with CRTCs 0, 1, 2. It can must be at 0 or 1 on CRTCs 3 and 4.
For compatibility reasons, it is strongly advised to always set bit 14 bit14 to 1 to select PAL. See [https://www.cpcwiki.eu/forum/news-events/release-of-amstrad-cpc-crtc-compendium-and-amazing-demo-rev-2021/msg239536 Discussion on the forum]
== PAL Type Detection ==
10 OUT &7F00,&C0:POKE &4000,&C0
20 OUT &7F00,&C7:POKE &4000,&C7:OUT &7F00,&C0
30 IF PEEK(&4000)=&C7 THEN PRINT"PAL chip absent/inactive":END
40 OUT &BC00,&F:OUT &3DFF,&C7
50 IF PEEK(&4000)=&C0 C7 THEN PRINT"PAL I/O layout on CRTC 0/1/2":END60 IF PEEK(&4000)=&C7 C0 THEN PRINT"PAL I/O layout on CRTC 3/4":END
70 PRINT"Error!"
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== See also ==
*CPC 464/664 cannot deal with A14/A15 for bank 0 Base 64k page like the 6128 does. So external RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]
*[[Gate Array and ASIC Pin-Outs]]
*[[Standard Memory Expansions]]
[[Category:Datasheet]]