Changes
Z80
,/* Instruction Execution Sequence */
#Operand Fetch (if needed)
#Memory Read / I/O Read (if needed)
#ExecutionOperation
#Memory Write / I/O Write (if needed)
#Loop (for block instructions only)
#At the end of every instruction, the IRQ (if IFF1 is active) and NMI pins are checked
For example, the instruction RL (IX+42) will doexecute as follow:
#M1 (4 t-states): Prefix fetch &DD
#M1 (4 t-states): Opcode fetch &CB (the second prefix)
#M2 (3 t-states): Operand fetch 42 (the displacement byte)
#M3 (5 t-states): Operand fetch &16 (the real opcode) and calculating the address IX+42
#M4 (4 t-states): Memory read at address IX+42 and then executionoperation
#M6 (3 t-states): Memory write at address IX+42
