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== I/O Ports Port Allocation Rules ==
Components use partial address decoding. It is therefore possible to send the same value to different components '''simultaneously''' by carefully using custom I/O ports. {|{{Prettytableclass="wikitable"! rowspan=2|Hardware device !! rowspan=2|Read/Write !! colspan=16|Port bits|width: 700px; font-size: 2em;}}! b15 !! b14 !! b13 !! b12 !! b11 !! b10 !! b9 !! b8 !! b7 !! b6 !! b5 !! b4 !! b3 !! b2 !! b1 !! b0|'''I-| [[Gate Array]] || Write only || 0 || 1 || - || - || - || - || - || - || - || - || - || - || - || - || - || -|-| [[PAL16L8|PAL]] (RAM configuration) || Write only || 0 || * || - || - || - || - || - || - || - || - || - || - || - || - || - || -|-| [[CRTC]] || Read/O'''Write ||'''Decoded as'''- ||'''0 || - || - || - || - || r1 || r0 || - || - || - || - || - || - || - || -|-| [[Upper ROM Bank Number|Upper ROM select]] || Write only || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || - || -|-| [[Printer Port''']] || Write only || - || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || -|-| [[8255|8255 PPI]] ||'''Read'''/Write ||'''- || - || - || - || 0 || - || r1 || r0 || - || - || - || - || - || - || - || -|-| Expansion Peripherals || Read/Write || - || - || - || - || - || 0 || x || x || x || x || x || x || x || x || x || x|} Legend:*"-" means this bit is ignored,*"0" means the bit must be set to "0" for the hardware device to respond,*"1" means the bit must be set to "1" for the hardware device to respond.*"r1" and "r0" mean a bit used to define a register* "*" Bit14 of the PAL port must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL. <br> == Official I/O Ports == The official ports are defined to eliminate conflict between devices, as follows: {| class="wikitable"!I/O!Decoded as!Port!Read!Write'''
|-
|#7FXX||%01xxxxxx xxxxxxxx||[[Gate Array]]||-||Write
|}
* The FDC is considered as an expansion peripheral. The three [[765 FDC]] floppy ports are contained in CPC 664/6128/Plus and DDI-1 only.
* The eight [[Amstrad Serial Interface]] ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.
* Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.
* As components use partial address decoding, it is therefore possible to send the same value to different components '''simultaneously''' by carefully using custom I/O ports.
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== Memory Mapped I/O Ports ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|'''!Mem'''||'''!Decoded as'''||'''!Port'''||'''!Read'''||'''!Write'''
|-
|#4000-7FFF||%01xxxxxx xxxxxxxx||ASIC - CPC+/GX4000 registers|| Read || Write
|}
The [[Writes to unused areas of the ASIC]] I/O page is defined as followsare not persisted. [https://www.cpcwiki.eu/forum/games/harrier-attack-reloaded/msg247703/#msg247703 Source]
{|{{Prettytable|width: 700px; font-size: 2em;}}! ADDR !! SIZE !! POR !! TYPE !! MNEM !! USE|-| 4000h || 100h || N || R/W || || Sprite 0 image data|-| 4100h || 100h || N || R/W || || Sprite 1 image data|-| ... || ... || ... || ... || ... || ...|-| 4F00h || 100h || N || R/W || || Sprite 15 image data|-| 5000h || || || || || (unused)|-| 6000h || 2 || N || R/W || X0 || Sprite 0 X position|-| 6002h || 2 || N || R/W || Y0 || Sprite 0 Y position|-| 6004h || 1 || Y || W || M0 || Sprite 0 magnification|-| 6005h || 3 || || || || (unused)|-| 6008h || 2 || N || R/W || X1 || Sprite 1 X position|-| 600Ah || 2 || N || R/W || Y1 || Sprite 1 Y position|-| 600Ch || 1 || Y || W || M1 || Sprite 1 magnification|-| 600Dh || 3 || || || || (unused)|-| ... || ... || ... || ... || ... || ...|-| 6078h || 2 || N || R/W || X15 || Sprite 15 X position|-| 607Ah || 2 || N || R/W || Y15 || Sprite 15 Y position|-| 607Ch || 1 || N || W || M15 || Sprite 15 magnification|-| 607Dh || 3 || || || || (unused)|-| 6080h || || || || || (unused)|-| 6400h || 2 || N || R/W || || Colour palette, pen 0|-| 6402h || 2 || N || R/W || || Colour palette, pen 1|-| ... || ... || ... || ... || ... || ...|-| 641Eh || 2 || N || R/W || || Colour palette, pen 15|-| 6420h || 2 || N || R/W || || Colour palette, border|-| 6422h || 2 || N || R/W || || Colour palette, sprite colour 1|-| 6424h || 2 || N || R/W || || Colour palette, sprite colour 2|-| ... || ... || ... || ... || ... || ...|-| 643Eh || 2 || N || R/W || || Colour palette, sprite colour 15|-| 6440h || || || || || (unused)|-| 6800h || 1 || Y || W || PRI || Programmable raster interrupt scan line|-| 6801h || 1 || Y || W || SPLT || Screen split scan line|-| 6802h || 2 || N || W || SSA || Screen split secondary start address|-| 6804h || 1 || Y || W || SSCR || Soft scroll control register|-| 6805h || 1 || N || W || IVR || Interrupt Vector (Bit 0 set to 1 on reset)|-| 6806h || || || || || (unused)|-| 6808h || 1 || || R || ADC0 || Analogue input channel 0|-| 6809h || 1 || || R || ADC1 || Analogue input channel 1|-| 680Ah || 1 || || R || ADC2 || Analogue input channel 2|-| 680Bh || 1 || || R || ADC3 || Analogue input channel 3|-| 680Ch || 1 || || R || ADC4 || Analogue input channel 4|-| 680Dh || 1 || || R || ADC5 || Analogue input channel 5|-| 680Eh || 1 || || R || ADC6 || Analogue input channel 6|-| 680Fh || 1 || || R || ADC7 || Analogue input channel 7|-| 6810h || || || || || (unused)|-| 6C00h || 2 || N || W || SAR0 || "DMA" channel 0 address pointer|-| 6C02h || 1 || N || W || PPR0 || "DMA" channel 0 pause prescaler|-| 6C03h || 1 || || || || (unused)|-| 6C04h || 2 || N || W || SAR1 || "DMA" channel 1 address pointer|-| 6C06h || 1 || N || W || PPR1 || "DMA" channel 1 pause prescaler|-| 6C07h || 1 || || || || (unused)|-| 6C08h || 2 || N || W || SAR2 || "DMA" channel 2 address pointer|-| 6C0Ah || 1 || N || W || PPR2 || "DMA" channel 2 pause prescaler|-| 6C0Bh || 4 || || || || (unused)|-| 6C0Fh || 1 || Y || R/W || DCSR || "DMA" control/status register|} POR column indicates whether a register has power on reset. A "N" indicates that See the contents of a register are undefined at power on. A colour in the palette is coded in 2 bytes:* For first byte, bit7..4 is blue value, bit3..0 is red value* For second byte, bit7..4 is ignored, bit3.[[ASIC]] page for details.0 is green value
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==Internal Links==
*[[Arnold V specs]]
*[[Arnold V Specs Revised]]
[[Category:Programming]] [[Category:CPC Internal Components]]