Difference between revisions of "RTC"

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(RTC Registers)
(RTC Registers)
Line 63: Line 63:
 
         7  VRT  Valid RAM and Time (1=Okay, 0=Battery Low)              (R)
 
         7  VRT  Valid RAM and Time (1=Okay, 0=Battery Low)              (R)
 
         6-0 0    Reserved (zero)
 
         6-0 0    Reserved (zero)
   0Eh..3Fh battery backed RAM (DS1287A, and other/newer chips)
+
   0Eh..3Fh battery backed RAM (HD146818, DS1287A, and other chips)
 
   40h..7Fh battery backed RAM (DS12887A, newer chip variants only)
 
   40h..7Fh battery backed RAM (DS12887A, newer chip variants only)
 
   80h..FFh reserved
 
   80h..FFh reserved

Revision as of 04:16, 2 April 2025

Real Time Clock (RTC)

PC compatible RTC chip

Usage in CPCs

Usage in SYMBiFACE II:Realtime clock:

 Uses a Dallas DS12887A RTC chip, mapped to ports:
 FD14h SYMBiFACE II Real Time Clock - DS12887A RTC Data  (R/W)
 FD15h SYMBiFACE II Real Time Clock - DS12887A RTC Index (W)

Usage in Dk'tronics Real Time Clock:

 Uses a HD146818 chip.
 Details on I/O addresses are unknown.

Usage in Aleste 520EX - I/O Ports:

 Uses a russian KR512WI1 chip (which is, according to the Aleste's 
 Manual) compatible to western MC146818 chips. 
 Connects to a 32.768kHz crystal.
 Connects to the PPI:
   PPI Port A.Bit0-7 = Data bus
   PPI Port C.Bit0   = Read/Write   (0=Write, 1=Read)
   PPI Port C.Bit1   = Index Access (0=No, 1=Access)
   PPI Port C.Bit2   = Data Access  (0=No, 1=Access)
 In the Aleste's Ext Port, the RTC must be enabled, and PSG and
 8253 must be disabled.

RTC Registers

 00h  Second       (00..59) ;\
 01h  Alarm second (00..59) ; these ten registers can be BCD or Binary
 02h  Minute       (00..59) ; (see Control B, Bit2=DM)
 03h  Alarm minute (00..59) ;
 04h  Hour         (00..23) ;  ;\in 24hour mode:
 05h  Alarm hour   (00..23) ;  ;/bit7=PM
 06h  Day of week  (01..07) ;
 07h  Day          (01..31) ;
 08h  Month        (01..12) ;
 09h  Year         (00..99) ;/
 0Ah  Control A
       7   UIP Update in Progress (0=Stable in next 244us, 1=Time changes) (R)
       6-4 DV  Oscillator control (must be 2 for normal operation)
       3-0 RS  Rate Selector for IRQ pin (not used by SYMBiFACE II)
 0Bh  Control B
       7   SET  Stop clock, to be set/cleared before/after writing to [0h..9h]
       6   PIE  Periodic Interrupt Enable (see Control A, RS)
       5   AIE  Alarm Interrupt Enable
       4   UIE  Update-Ended Interrupt Enable (aka Seconds Interrupt)
       3   SQWE Square-Wave Enable (see Control A, RS)
       2   DM   Data Mode for [00h..09h] (0=BCD, 1=Binary)
       1   24H  24-Hour Mode             (0=12h with AM/PM, 1=24h)
       0   DSE  Daylight Saving Enable   (0=No, 1=Uses hardcoded timezone)
 0Ch  Control C (read-only, automatically reset to zero after reading)
       7   IRQF Interrupt Request Flag (1 on PIE,AIE,UIE, 0 after read) (R)
       6   PF   Periodic Interrupt Flag     (see Control A, RS)         (R)
       5   AF   Alarm Interrupt Enable Flag                             (R)
       4   UF   Update-Ended Interrupt Flag (aka Seconds Interrupt)     (R)
       3-0 0    Reserved (zero)
 0Dh  Control D (read-only)
       7   VRT  Valid RAM and Time (1=Okay, 0=Battery Low)              (R)
       6-0 0    Reserved (zero)
 0Eh..3Fh battery backed RAM (HD146818, DS1287A, and other chips)
 40h..7Fh battery backed RAM (DS12887A, newer chip variants only)
 80h..FFh reserved

Other chips