Programmable Array Logic (PAL). Not to be confused with PAL, the colour encoding system for analog televisions. The CPC6128 second bank page of 64K 64KB RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.
On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.
== Fixed version (Gerald) ==Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.<br>
A14OUT = !( !A14 # !A15 & !Q0 & Q2 ); A15OUT = !( !A15 & !A14 # !A15 & !Q1 # !A15 & !Q0 & !Q2 ); Q0 IC Models used in CPC = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR # !D7ANDD6 & nRESET & Q0 # nRESET & A15 & Q0 # nRESET & nIOWR & Q0 ); Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR # !D7ANDD6 & nRESET & Q1 # nRESET & A15 & Q1 # nRESET & nIOWR & Q1 ); Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR # !D7ANDD6 & nRESET & Q2 # nRESET & A15 & Q2 # nRESET & nIOWR & Q2 ); nCAS0 = ( nCAS # RAMDIS & !nCPU & nCAS0 # !A15 & A14 & !nCPU & Q2 & nCAS0 # A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0 # !nCPU & !Q0 & Q1 & !Q2 & nCAS0 # !nCAS1 ); nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0 # !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0 # !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0 # !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1 # !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1 # !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );These are the ones known to be used in the CPC by looking at pictures of CPC mainboards:
* HAL16L8ACN [[Filehttps:CPC6128//www.JED]cpcwiki.eu/imgs/6/67/CPC6128_PCB_Top_%28Z70290_MC0020F%29.jpg Source] * PAL16L8ACN [https: Fixed version of Amstrad 40031 GAL replacement//www.cpcwiki.eu/imgs/4/4e/CPC6128_PCB_Top_%28Z70290_MC0020G%29.jpg Source]
[[File:CPC6128.hex]] : Fixed version of They both wear the same Amstrad part number 40031 GAL replacement. On the Amstrad chassis schematic diagram, Hex Intel versionthis part is numbered 40030.[https://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png Source]
== Initial replacement equation (Porchy) ==<br>
The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:== PAL I/O port ==
A15OUT = (!X2 & !X1 & A14 # !X3 & !X2 & A14 # A15); !X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0 # !X1 & RESET & IOWR # !X1 & !D7ANDD6 & RESET # !X1 & A15 & RESET); !X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1 # !X2 & RESET & IOWR # !X2 & !D7ANDD6 & RESET # !X2 & A15 & RESET); !X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2 # !X3 & RESET & IOWR # !X3 & !D7ANDD6 & RESET # !X3 & A15 & RESET); !CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0 # !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0 # X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0 # !NCAS & CAS0 & !CAS1); !CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1 # X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1 # !X3 & A15 & !NCAS & !RAMDIS & CAS1 # !X1 & !A14 & !NCAS & !RAMDIS & CAS1 # !X3 & !A14 & !NCAS & !RAMDIS & CAS1 # !NCAS & !RAMDIS & CPU & CAS1 # !NCAS & !CAS0 & CAS1); A14OUT = (A15 & A14 # !X1 & A14 # X3 & A14);Note that no settings are stored in the Gate Array itself regarding the MMR register. But the PAL and Gate Array share an I/O port address so that it appears to be the same chip to the programmer.
Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3/4. It must be at 1 on CRTCs 0/1/2 (The result is not guaranteed). For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL. Furthermore, if bit14=0 then CRTC will be selected too. The recommended I/O port address is &7Fxx. Moreover, the PAL only respond to I/O Write requests while the Gate Array will respond no matter what the Read/Write I/O signal is. [[Filehttps:Amstrad6128//www.jedgrimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]] Original JED File posted on CPCWiki Forum <br>
== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the (even in C3 mode). The [[Gate Array ]] can only access the unmapped Base 64k page of RAM.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|!colspan=2|'''MMR'''||!colspan=3|'''64K page'''||'''!S'''||!colspan=2|'''MM'''||!colspan=4 style="text-align: center;"|'''CPU Memory Mapping'''
|-
|'''!7'''|'''!6'''|'''!5'''|'''!4'''|'''!3'''|'''!2'''|'''!1'''|'''!0'''|style="text-align: center;"|'''!&0000-&3fff'''|style="text-align: center;"|'''!&4000-&7fff'''|style="text-align: center;"|'''!&8000-&bfff'''|style="text-align: center;"|'''!&c000-&ffff'''
|-
|1
|}
== PAL I/O port ==On a standard 128k machine (unexpanded), bits5..3 are ignored. Page will always be fixed to Page 0.
Note that no settings are stored in the Gate Array regarding register 3, but the PAL and Gate Array share an I/O port address.<br>
Bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1, 2. It can be at 0 or 1 on CRTCs 3 and 4.=== Page order ===
RAM expansions are not required to conform to any page order. For compatibility reasonsexample, it the [[Dk'tronics Silicon Disc]] is strongly advised to always set bit 14 to 1 a 256k RAM expansion that provides Pages 4 to select PAL7.
RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx. Given this diversity of RAM expansions, [[SymbOS]] does the right thing by testing each 64k page individually to detect the available RAM. <br> === RAM mode &C3 === The CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions can differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/news-events/release-of-amstrad-cpc-crtchardware/464-compendiumpreasic-andc3-amazingram-democonfiguration-revand-rom-20217/msg239536 Discussion on the forum]and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]. <br>
== PAL Type Detection ==
20 OUT &7F00,&C7:POKE &4000,&C7:OUT &7F00,&C0
30 IF PEEK(&4000)=&C7 THEN PRINT"PAL chip absent/inactive":END
40 OUT &BC00,&F:OUT &3DFF3FFF,&C750 IF PEEK(&4000)=&C0 C7 THEN PRINT"IO Bit14=0 PAL I/O layout on CRTC selected" ELSE PRINT"IO Bit14=0/1/2PAL not selected":END60 OUT &7F00,&C0:POKE &C000,&C070 OUT &7F00,&C3:POKE &4000,&C3:OUT &7F00,&C080 IF PEEK(&4000C000)=&C7 C3 THEN PRINT"PAL I/O layout on CRTC 3/4Valid RAM mode &C3":END70 ELSE PRINT"Error!Invalid RAM mode &C3"
</pre>
== See also ==<br>
*CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-== PAL andPre-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]ASIC ==
*[[Gate Array and ASIC PinThe PAL component is integrated inside the Pre-Outs]]ASIC chip. But it is disabled by default on the CPC 464.
It is possible to enable it by doing an hardware modification explained in that article: [[Arnold4]]
<br>
== PAL and ASIC ==
The PAL component is integrated inside the ASIC chip. But it is disabled by default on the 464 Plus and GX4000. [https://www.cpcwiki.eu/forum/news-events/announcing-sonic-gx-a-new-episode-of-sonic-the-hedgehog-for-amstrad-gx-4000/msg248436/#msg248436 Source]
Besides, most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source]
The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way.
Unfortunately, memory expansions designed for the classic CPC does not take this into account. For some of them, because they were designed before the Amstrad Plus ASIC existed, and for some, the designers didn't think of it or decided it was not important. As a result, these extensions can enter in conflict with the ASIC, which will result, at best, in software crashes, and at worst, in '''damage to the hardware'''.
Software that is known to hit this problem with existing memory expansions:
*[https://www.cpc-power.com/index.php?page=detail&num=14940 CRTC3 demo]
*[https://soundtrackerdma.cpcscene.net/doku.php?id=en:download Soundtracker DMA]
<br>
== Signals used for RAM management ==
The following signals are used for RAM management and are available on the expansion connector.
=== RAMDIS ===
(Internal RAM Disable; Input to Internal RAM)
When RAMDIS="1" the internal RAM of the CPC/CPC+/KC Compact is forced inactive.
e.g. a ram-expansion device would use this signal to override the internal RAM selection with the RAM on the device. The internal RAM would be forced inactive, and the RAM on the ram-expansion would be actived.
=== /RAMRD ===
(RAM Read; Output from Gate-Array)
When /RAMRD="0" a ram read operation is active. This signal is generated by the Gate-Array. This signal will be "0" when:
* A15=A14="0" and bit 2 of the Gate-Array rom configuration register is set to 1. (lower ROM disable)
* A15=A14="1" and bit 3 of the Gate-Array rom configuration register is set to 1. (upper ROM disable)
* A15 is not equal to A14.
<br>
== Initial replacement equation (Porchy) ==
The following equations were worked out by Porchy (member on CPCWiki Forum) to program replacements:
A15OUT = (!X2 & !X1 & A14
# !X3 & !X2 & A14
# A15);
!X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0
# !X1 & RESET & IOWR
# !X1 & !D7ANDD6 & RESET
# !X1 & A15 & RESET);
!X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1
# !X2 & RESET & IOWR
# !X2 & !D7ANDD6 & RESET
# !X2 & A15 & RESET);
!X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2
# !X3 & RESET & IOWR
# !X3 & !D7ANDD6 & RESET
# !X3 & A15 & RESET);
!CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0
# !NCAS & CAS0 & !CAS1);
!CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1
# X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1
# !X3 & A15 & !NCAS & !RAMDIS & CAS1
# !X1 & !A14 & !NCAS & !RAMDIS & CAS1
# !X3 & !A14 & !NCAS & !RAMDIS & CAS1
# !NCAS & !RAMDIS & CPU & CAS1
# !NCAS & !CAS0 & CAS1);
A14OUT = (A15 & A14
# !X1 & A14
# X3 & A14);
[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum
<br>
== Fixed version (Gerald) ==
Original version from Porchy suffers from a bad handling of the RAMDIS signal. It caused screen artefact when accessing an external RAM expansion.
A14OUT = !( !A14
# !A15 & !Q0 & Q2 );
A15OUT = !( !A15 & !A14
# !A15 & !Q1
# !A15 & !Q0 & !Q2 );
Q0 = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q0
# nRESET & A15 & Q0
# nRESET & nIOWR & Q0 );
Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q1
# nRESET & A15 & Q1
# nRESET & nIOWR & Q1 );
Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q2
# nRESET & A15 & Q2
# nRESET & nIOWR & Q2 );
nCAS0 = ( nCAS
# RAMDIS & !nCPU & nCAS0
# !A15 & A14 & !nCPU & Q2 & nCAS0
# A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS1 );
nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0
# !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1
# !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1
# !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );
[[File:CPC6128.JED]] : Fixed version of Amstrad 40031 GAL replacement
[[File:CPC6128.hex]] : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version.
<br>
== Internal PAL on CPC 6128 ==
[[File:Amstrad.cpc6128.pal.ga.jpg]]
<br>
== 576KB vs 640KB total ==
Bits 3, 4, 5 allow to define up to 8 pages of 64K for RAM expansion at a given address range in addition to the 64K base RAM. The internal second 64K RAM bank of the CPC 6128 is usually disabled when a RAM expansion is used, as the 64K enhanced RAM in the 6128 would use the same address range (&7Fxx) as the first 64K of the RAM expansion. This gives you 576K of total RAM on a CPC.
However, if the RAM expansion decodes the [[Standard_Memory_Expansions#Extended_1M-4M_Expansions_.28RAM7.2FYarek-style.29|A8 address line]], you can access the internal second RAM bank of the 6128 from another range (&7Exx). The [[X-MEM]] and [[CPC_iRAM#CPC_iRAM.2F640|iRAM/640]] expansions implement this and therefore can provide 640K of total RAM. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/extram-512kb-to-640kb-for-cpc6128-on-one-dip20-chip-slg46533v-dip/msg247763/#msg247763 Source]
<br>
== 4MB RAM expansions ==
Beware about 4MB RAM expansions. The upper 2MB (Port 7Bxxh, 7Axxh, 79xxh, 78xxh) of a 4MB RAM expansion can conflict with other hardware as setting A10 to 0 is also used for many hardware expansions.
See the [[Default I/O Port Summary|I/O Port Allocation Rules]] to understand why.
The practical safe maximum on Amstrad CPC with [[Standard Memory Expansions]] is 2MB.
<br>
== Related pages ==
*[[media:Programmable Array Logic PAL16L8ACN.pdf|PAL16L8 datasheet]]
*[[Gate Array and ASIC Pin-Outs]]
*[[Standard Memory Expansions]]
[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]][[Category: Memory expansions]][[Category:Programming]] [[Category:Datasheet]]