== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the (even in C3 mode). The [[Gate Array]] can only access the unmapped Base 64k page of RAM.
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On a standard 128k machine (unexpanded), bits5..3 are ignored. Page will always be fixed to Page 0.
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=== Page order ===
RAM expansions are not required to conform to any page order. For example, the [[Dk'tronics Silicon Disc]] is a 256k RAM expansion that provides Pages 4 to 7.
RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx.
Given this diversity of RAM expansions, [[SymbOS]] does the right thing by testing each 64k page individually to detect the available RAM.
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The CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does.
So external RAM expansions can differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion].
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== Integrated PAL in and Pre-ASIC ==
The PAL component is integrated inside the Pre-ASIC chip. But it is disabled by default on the CPC 464.
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== PAL and ASIC compatibility ==
Most The PAL component is integrated inside the ASIC chip. But it is disabled by default on the 464 Plus and GX4000. [https://www.cpcwiki.eu/forum/news-events/announcing-sonic-gx-a-new-episode-of-sonic-the-hedgehog-for-amstrad-gx-4000/msg248436/#msg248436 Source] Besides, most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source]
The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way.
When RAMDIS="1" the internal RAM of the CPC/CPC+/KC Compact is forced inactive.
e.g. a ram-expansion device would use this signal to override the internal RAM selection with the ram RAM on the device. The internal RAM would be forced inactive, and the ram RAM on the ram-expansion would be actived.
=== /RAMRD ===
(Ram RAM Read; Output from Gate-Array)
When /RAMRD="0" a ram read operation is active. This signal is generated by the Gate-Array. This signal will be "0" when:
* A15=A14="0" and bit 2 of the Gate-Array rom configuration register is set to 1. (lower rom ROM disable)* A15=A14="1" and bit 3 of the Gate-Array rom configuration register is set to 1. (upper rom ROM disable)
* A15 is not equal to A14.
== Initial replacement equation (Porchy) ==
The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:
A15OUT = (!X2 & !X1 & A14
== Fixed version (Gerald) ==
Original version from Porchy suffer suffers from a bad handling of the RAMDIS signal. This cause It caused screen artefact when accessing an external extension RAM like XMEMexpansion.
A14OUT = !( !A14
== 576KB vs 640KB total ==
Bits 3, 4, 5 allow to define up to 8 pages of 64K for RAM expansion at a given address range. This does not affect in addition to the 64K base RAM. The internal second 64K RAM bank of the CPC 6128 is usually disabled when a RAM expansion is used, as the 64K enhanced RAM in the 6128 would use the same address range (&7Fxx) as the first 64K of the RAM expansion. This gives you 576K of total RAM on a CPC.
The However, if the RAM expansion decodes the [[Standard_Memory_Expansions#Extended_1M-4M_Expansions_.28RAM7.2FYarek-style.29|A8 address line]], you can access the internal second RAM bank of the CPC 6128 adds 1x 64K, which is usually disabled by expansions, because at the same address from another range (&7Fxx7Exx).The [[X-MEM]] and [[CPC_iRAM#CPC_iRAM.2F640|iRAM/640]] expansions implement this and therefore can provide 640K of total RAM. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/extram-512kb-to-640kb-for-cpc6128-on-one-dip20-chip-slg46533v-dip/msg247763/#msg247763 Source]
But, if the expansion <br> == 4MB RAM decodes the A8 address line, you can still access this page from another range expansions == Beware about 4MB RAM expansions. The upper 2MB (&7Exx)Port 7Bxxh, like [[X-MEM]] 7Axxh, 79xxh, 78xxh) of a 4MB RAM expansion doescan conflict with other hardware as setting A10 to 0 is also used for many hardware expansions. See the [https:[Default I/O Port Summary|I/www.cpcwiki.eu/forum/amstrad-cpc-hardware/extram-512kb-O Port Allocation Rules]] to-640kb-for-cpc6128-understand why. The practical safe maximum on-one-dip20-chip-slg46533v-dip/msg247763/#msg247763 SourceAmstrad CPC with [[Standard Memory Expansions]] is 2MB.
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== Related pages ==
*[[media:Programmable Array Logic PAL16L8ACN.pdf|PAL16L8 datasheet]]
*[[Gate Array and ASIC Pin-Outs]]
*[[Standard Memory Expansions]]