Changes
Z80
,/* M-cycles and T-states */
**The instruction RST t has an M1 cycle consisting of 5 T-states instead of the usual 4.
**The CALL cc,nn instruction has an extra T-state inserted in M3 depending if cc is true or not.
Every place the Z80 manual shows a memory read taking more than 3 clocks, or an opcode fetch/decode taking more than 4 clocks, it should be interpreted as "standard read or fetch cycle with (n - 3) or (n - 4) internal operations after. [https://forums.nesdev.org/viewtopic.php?p=179001#p179001 Source]
{| class="wikitable"
