To resolve this, MOS Technology stopped producing the 6501 and introduced the 6502. While the 6502 was similar in design to the 6501 and 6800, it was no longer pin-compatible with the 6800, avoiding further legal issues.
Importantly, the 6502 had a much lower price point, which made it highly attractive to electronics manufacturers. Priced initially at just $25, the 6502 drastically undercut the Motorola 6800 and other competing processors like the Intel 8080, which were priced around $179 at the time. Motorola must have learnt from this lesson when they decided to sell the 68000 at $15 to Apple for the Macintosh in 1984.
<br>
* The Z80 has more registers but has to do pretty much everything with them whilst the 6502 can directly use the first 256 bytes of memory for those jobs.
This shows The 6502 and Z80 exemplify the design fundamental differences between the 6502 what would become known as RISC and Z80CISC architectures. The 6502 focused on efficiencywas designed with a streamlined, using its limited transistor budget for the ALU and fast memory accessminimal instruction set to achieve high execution speed. In contrastThe Z80, on the Z80 neglected these and used other hand, incorporated a larger, more transistors for extra registers and complex instructions. However, these Z80's features, like the alternate register instruction set, register pairs aiming to make assembly programming more accessible and 16-bit stack, make it easier to develop complex softwarecreate more compact programs.
The 6502 comes in a 40-pin DIP package. It has been produced by various manufacturers and used in a wide range of applications, from gaming consoles like the [[Atari 2600|Atari VCS]], [[Atari Lynx]], [[Nintendo Entertainment System]] and [[PC-Engine]] to personal computers like the [[Apple II]], [[BBC Micro]], [[Atari XL]], [[Oric]], [[VIC20]] and [[Commodore 64]].
<br>
== Registers Register File ==
{| class="wikitable" style="white-space: nowrap;"
* bit0 - CF - Carry Flag: 1 on unsigned overflow
|| Flags are affected by most operations.
The BF is bit does not a physical flag implemented in a registeractually exist inside the 6502. It The BF bit only appears on exists in the status flag byte pushed to the stack when . When the P register flags are restored (via PLP or RTI), the BF bit is pushed to itdiscarded.
PHP (Push Processor Status) and PLP (Pull Processor Status) can be used to set or retrieve P directly via the stack.
|}
SeeThe 6502 also has internal latches and buffers used for address handling and instruction execution. For example: [https*ABL/ABH:Address Bus Low//www.rightoHigh, latches for the address bus.com/2012/12*AI/BI: Input Registers for the-6502-overflow-flag-explainedALU.*IR: Instruction Register, holds the fetched instruction opcode byte while the CPU decodes and executes it.html The 6502 overflow flag explained mathematically]
<br>
== Decimal Mode ==
BCD operations are limited to addition and subtraction using the Decimal Mode allows ADC and SBC instructionsto use Binary-Coded Decimal (BCD), where each nibble (4 bits) represents a decimal digit (0-9), instead of binary.
On NMOS, when Decimal Mode is on, the ADC and SBC instructions update NF, VF and ZF based on the binary result before the decimal correction is applied. Only CF is updated correctly. On CMOS, all the flags are updated correctly, at the cost of 1 additional cycle.
== Pipelining ==
The 6502 CPU uses some sort We have to dispel the myth of pipeliningin the 6502. If an instruction does not store data we analyze its operation in memory on its last cyclehalf-cycles, the processor can fetch the opcode of the next we see that instruction while executing the last cycle. This execution is very primitive as the 6502 does not have an instruction cache nor even a prefetch queue. It relies on RAM tightly bound to hold all program informationmemory operations without any overlap between different instructions.
As an exampleEach instruction follows a rigid sequence of steps, with no ability to fetch the next instruction EOR #$FF truly takes 3 cycles:* On while executing the first cycle, current one. This means that the opcode $49 will be fetched* During the second cycle the processor decodes the opcode and fetches the parameter #$FF* On the third cycle, the processor will perform the operation and store the result CPU cannot prefetch opcodes or operands ahead of time in register A, but simultaneously it fetches the opcode for the next instructionway a pipelined architecture would.
This is If we invert our perspective and consider ϕ2 as the first half-cycle and ϕ1 as the second, it becomes evident why pipelining does not exist on the EOR instruction effectively takes only 2 cycles6502.
However, this pipelining only makes sense when looking at full cycles. If we break it down into half-cycles, there's no actual overlap. In fact, it's the other way around. If the previous instruction ends with a memory write, the CPU has to wait for a half-cycle before fetching being able to fetch the next instruction on the next ϕ2 half-cycle.
<br>
== Adressing Modes ==
The 6502 uses only one addressing mode per instruction.
{| class="wikitable"
The Zero Page on the 6502 is a special area of memory from addresses $0000 to $00FF that act like pseudo registers. The 6502 provides optimized instructions that operate more efficiently when using addresses within the Zero Page.
Fun fact: the TMS9900 CPU took this further, and had by having no onboard registers (other than , except PC & status register). Everything was in RAM.
<br>
== NMOS 6502 Instruction Set Execution Sequence ==
For an instruction to fully execute, the 6502 goes through these key phases in order: #Opcode Fetch#Operand Fetch (if needed)#Memory Read / I/O Read (if needed)#Operation#Memory Write / I/O Write (if needed)#At the end of every instruction, the IRQ (if the interrupt disable flag is clear) and NMI pins are checked. As an example, let M[$42]=$80, M[$43]=$10 and Y= Standard instructions $F1. Then the instruction LDA ($42),Y will execute as follow, with ϕ2 as the first half-cycle and ϕ1 as the second half-cycle:*T0: Fetch opcode $B1 (LDA (zp),Y) from memory then increment PC*T1: Fetch operand byte $42 (zero page pointer address) then increment PC*T2: Get low byte from zero page ($80) then increment the zero page address*T3: Get high byte from next zero page location ($10) then add the Y register value ($F1) to $1080*T4: Garbage fetch from memory address $1071 then handle page boundary crossing (since $1080 + $F1 crosses a page)*T5: Read the value from memory address $1171 into the accumulator then no operation in the last half-cycle <br> == NMOS 6502 Instruction Set ==
Cycles are shown in parenthesis for each opcode. p=1 if page is crossed. t=1 if branch is taken.
=== ALU instructions ===
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! colspan=13|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description
|-
! ''No arg'' !! A !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C
|-
| ADC BIT || || || 69 (2) || 6D 2C (4) || 7D (4+p) || 79 (4+p) || || 65 24 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || - || Z || C - || A + ∧ M + CF , M<sub>7</sub> → ANF, CF M<sub>6</sub> → VF || Add Memory to Accumulator with Carrytest BITs
|-
| AND || || || 29 (2) || 2D (4) || 3D (4+p) || 39 (4+p) || || 25 (3) || 35 (4) || || 21 (6) || 31 (5+p) || || N || - || - || - || - || Z || - || A ∧ M → A || "bitwise AND" Memory with Accumulatoraccumulator
|-
| ASL EOR || || 0A || 49 (2) || 4D (4) || 0E 5D (64+p) || 1E 59 (74+p) || || || 06 45 (53) || 16 55 (64) || || 41 (6) || 51 (5+p) || || N || - || - || - || - || Z || C - || CF ← /M<sub>7</sub>...A ⊻ M<sub>0</sub>/ ← 0 → A || Arithmetic Shift Leftbitwise Exclusive OR
|-
| BCC ORA || || || 09 (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || || 90 11 (2+t5+p) || - || - N || - || - || - || - Z || - || Branch on CF = 0 A ∨ M → A || Branch on Carry Clearbitwise OR with Accumulator
|-
| BCS |ADC | || || |69 (2) | |6D (4) | |7D (4+p) | |79 (4+p) | || |65 (3) | |75 (4) | || |61 (6) | || B0 71 (2+t5+p) || - || - N || - V || - || - || - Z || - C || Branch on A + M + CF → A, CF = 1 || Branch on ADd with Carry Set
|-
| BEQ |SBC | || || |E9 (2) | |ED (4) | |FD (4+p) | |F9 (4+p) | || |E5 (3) | |F5 (4) | || |E1 (6) | || F0 F1 (2+t5+p) || - || - N || - V || - || - || - Z || - C || Branch on ZF = A - M - (1 - CF) → A || Branch on Result ZeroSuBtract with Carry
|-
| BIT CMP || || || C9 (2) || 2C CD (4) || DD (4+p) || D9 (4+p) || || 24 C5 (3) || D5 (4) || || C1 (6) || D1 (5+p) || || N || V || - || - || - || Z || - C || A ∧ - M, M<sub>7</sub> → NF, M<sub>6</sub> → VF || Test Bits in Memory with AccumulatorCoMPare accumulator
|-
| BMI CPX || || || E0 (2) || EC (4) || || || || E4 (3) || || || || || 30 (2+t+p) || - N || - || - || - || - Z || - C || X - M || Branch on NF = 1 || Branch on Result MinusComPare X register
|-
| BNE CPY || || || C0 (2) || CC (4) || || || || C4 (3) || || || || || D0 (2+t+p) || - N || - || - || - || - Z || - C || Y - M || Branch on ZF = 0 || Branch on Result Not ZeroComPare Y register
|-
| BPL ASL || || 0A (2) || || 0E (6) || 1E (7) || || || 06 (5) || 16 (6) || || || || 10 (2+t+p) || - N || - || - || - || - Z || - C || - || Branch on NF = CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← 0 || Branch on Result PlusArithmetic Shift Left
|-
| BRK LSR || 00 || 4A (72) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || 0 || - || - || 1 || - || 1 Z || - C || - || PC + 2↓, [FFFE] 0 → PCL, [FFFF] /M<sub>7</sub>...M<sub>0</sub>/ → PCH CF || Force InterruptLogical Shift Right
|-
| BVC ROL || || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || 36 (6) || || || || 50 (2+t+p) || - N || - || - || - || - Z || - || - C || Branch on VF = CF ← /M<sub>7</sub>...M<sub>0 </sub>/ ← CF || Branch on Overflow ClearROtate Left
|-
| BVS ROR || || 6A (2) || || 6E (6) || 7E (7) || || || 66 (5) || 76 (6) || || || || 70 (2+t+p) || - N || - || - || - || - Z || - || - C || Branch on VF = 1 CF → /M<sub>7</sub>...M<sub>0</sub>/ → CF || Branch on Overflow SetROtate Right
|-
| CLC DEC || 18 (2) || || || CE (6) || DE (7) || || || C6 (5) || D6 (6) || || || || || - N || - || - || - || - Z || - || 0 || 0 M - 1 → CF M || Clear Carry FlagDECrement memory
|-
| CLD INC || D8 (2) || || || EE (6) || FE (7) || || || E6 (5) || F6 (6) || || || || || - N || - || - || 0 || - || - Z || - || 0 M + 1 → DF M || Clear Decimal ModeINCrement memory
|-
| CLI DEX || 58 CA (2) || || || || || || || || || || || || || - N || - || - || - || 0 Z || - || X - || 0 1 → IF X || Clear Interrupt DisableDEcrement X
|-
| CLV DEY || B8 88 (2) || || || || || || || || || || || || || - N || 0 - || - || - || - Z || - || Y - || 0 1 → VF Y || Clear Overflow FlagDEcrement Y
|-
| CMP INX || E8 (2) || || C9 (2) || CD (4) || DD (4+p) || D9 (4+p) || || C5 (3) || D5 (4) || || C1 (6) || D1 (5+p) || || N || - || - || - || - || Z || C - || A - M X + 1 → X || Compare Memory and AccumulatorINcrement X
|-
| CPX INY || C8 (2) || || E0 (2) || EC (4) || || || || E4 (3) || || || || || || N || - || - || - || Z || - || Z Y + 1 → Y || C INcrement Y|} === Move instructions === {| X class="wikitable" style="white- M || Compare Index Register X To Memoryspace: nowrap;"
|-
! rowspan=2| CPY Mnemonic !! colspan=12|Addressing Modes !! colspan=6| Flags !! rowspan=2|| || C0 (Operation !! rowspan=2) || CC (4) || || || || C4 (3) || || || || || || N || - || - || - || - || Z || C || Y - M || Compare Index Register Y To MemoryDescription
|-
| DEC || || || || CE ! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! (6$nnnn) || DE !! $nn !! $nn,X !! $nn,Y !! (7$nn,X) || || || C6 !! (5$nn) || D6 (6) || || || || || ,Y !! rel !! N || - || - || - || - || !! V !! D !! I !! Z || - || M - 1 → M || Decrement Memory By One!! C
|-
| DEX LDA || CA || A9 (2) || AD (4) || BD (4+p) || B9 (4+p) || || A5 (3) || B5 (4) || || A1 (6) || || || B1 (5+p) || || N || - || - || - || - || Z || - || X - 1 M → X A || Decrement Index Register X By OneLoaD Accumulator
|-
| DEY LDX || 88 || A2 (2) || AE (4) || || BE (4+p) || || A6 (3) || || || || B6 (4) || || || || N || - || - || - || - || Z || - || Y - 1 M → Y X || Decrement Index Register Y By OneLoaD X register
|-
| EOR LDY || || || 49 A0 (2) || 4D AC (4) || 5D BC (4+p) || 59 (4+p) || || 45 A4 (3) || 55 B4 (4) || || 41 (6) || 51 (5+p) || || N || - || - || - || - || Z || - || A ⊻ M → A Y || "Exclusive OR" Memory with AccumulatorLoaD Y register
|-
| INC STA || || || 8D (4) || EE 9D (65) || FE 99 (75) || || || E6 85 (53) || F6 95 (64) || || 81 (6) || 91 (6) || || N - || - || - || - || - || Z || - || M + 1 A → M || Increment Memory By OneSTore Accumulator
|-
| INX STX || E8 (2) || || 8E (4) || || || || 86 (3) || || 96 (4) || || || || || N - || - || - || - || - || Z || - || X + 1 → X M || Increment Index Register STore X By Oneregister
|-
| INY STY || C8 (2) || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || || N - || - || - || - || - || Z || - || Y + 1 → Y M || Increment Index Register STore Y By Oneregister
|-
| JMP TAX || AA (2) || || || 4C (3) || || || 6C (5) || || || || || || N || - || - || - || - Z || - || - || - || [PC + 1] → PCL, [PC + 2] A → PCH X || JumpTransfer A to X
|-
| JSR TXA || 8A (2) || || || 20 (6) || || || || || || || || || N || - || - || - || - Z || - || - || - || PC + 2↓, [PC + 1] → PCL, [PC + 2] X → PCH A || Jump To SubroutineTransfer X to A
|-
| LDA TAY || || || A9 A8 (2) || AD (4) || BD (4+p) || B9 (4+p) || || A5 (3) || B5 (4) || || A1 (6) || B1 (5+p) || || N || - N || - || - || - || Z || - || M → A → Y || Load Accumulator with MemoryTransfer A to Y
|-
| LDX TYA || || || A2 98 (2) || AE (4) || || BE (4+p) || || A6 (3) || || B6 (4) || || || || N || - N || - || - || - || Z || - || M Y → X A || Load Index Register X From MemoryTransfer Y to A
|-
| LDY TSX || || || A0 BA (2) || AC (4) || BC (4+p) || || || A4 (3) || B4 (4) || || || || || N || - N || - || - || - || Z || - || M S → Y X || Load Index Register Y From MemoryTransfer Stack pointer to X
|-
| LSR TXS || || 4A 9A (2) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || 0 - || - || - || - || - || Z - || C || 0 → /M<sub>7</sub>...M<sub>0</sub>/ X → CF S || Logical Shift RightTransfer X to Stack pointer
|-
| NOP PLP || EA 28 (24) || || || || || || || || || || || || N || - V || - D || - I || - Z || - C || - || - || No operation (S)↑ → P || No OperationPuLl Processor status
|-
| ORA PLA || || || 09 68 (24) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || N || - N || - || - || - || Z || - || A ∨ M (S)↑ → A || "OR" Memory with PuLl Accumulator
|-
| PHA PHP || 48 08 (3) || || || || || || || || || || || || || - || - || - || - || - || - || - || A↓ P↓ || Push Accumulator On StackPusH Processor status
|-
| PHP PHA || 08 48 (3) || || || || || || || || || || || || - || - || - || 1 || - || - || - || - A↓ || P↓ PusH Accumulator|} === Jump and Flag instructions === {| Push Processor Status on Stackclass="wikitable" style="white-space: nowrap;"
|-
! rowspan=2| PLA Mnemonic !! colspan=12|Addressing Modes !! colspan=6| 68 (4) Flags !! rowspan=2|Operation !! rowspan=2| || || || || || || || || || || || || N || - || - || - || - || Z || - || (S)↑ → A || Pull Accumulator From StackDescription
|-
| PLP || 28 ! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! (4$nnnn) || || || || || || || || || || || || || !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N || !! V || - || !! D || !! I || !! Z || !! C || (S)↑ → P || Pull Processor Status From Stack
|-
| ROL JMP || || 2A (2) || || 2E 4C (6) || 3E (73) || || || 26 6C (5) || 36 (6) || || || || || N || - || - || - || - || Z - || C - || CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← CF [PC + 1] → PCL, [PC + 2] → PCH || Rotate One Bit Left (Memory or Accumulator)JuMP
|-
| ROR JSR || || 6A (2) || || 6E 20 (6) || 7E (7) || || || 66 (5) || 76 (6) || || || || || N - || - || - || - || - || Z - || C || CF PC + 2↓, [PC + 1] → /M<sub>7</sub>...M<sub>0</sub>/ PCL, [PC + 2] → CF PCH || Rotate One Bit Right (Memory or Accumulator)Jump to SubRoutine
|-
| RTI RTS || 40 60 (6) || || || || || || || || || || || || - || N - || V - || - || D - || I || Z || C - || (S)↑ → PPCL, (S)↑ → PCLPCH, (S)↑ PC + 1 → PCH PC || Return From InterruptReTurn from Subroutine
|-
| RTS RTI || 60 40 (6) || || || || || || || || || || || || N || - V || - D || - I || - Z || - || - || - C || (S)↑ → PCLP, (S)↑ → PCHPCL, PC + 1 (S)↑ → PC PCH || Return From SubroutineReTurn from Interrupt
|-
| SBC BRK || || || E9 00 (27) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (6) || F1 (5+p) || || N || V - || - || - || - 1 || Z - || C - || A - M - (1 - CF) PC + 2↓, [FFFE] → PCL, [FFFF] → A PCH || Subtract Memory from Accumulator with BorrowBReaK
|-
| SEC SEI || 38 78 (2) || || || || || || || || || || || || || - || - || - || - 1 || - || - || 1 || 1 → CF IF || Set Carry FlagSEt Interrupt flag
|-
| SED CLI || F8 58 (2) || || || || || || || || || || || || || - || - || - || 1 || - 0 || - || - || 1 0 → DF IF || Set Decimal ModeCLear Interrupt flag
|-
| SEI SEC || 78 38 (2) || || || || || || || || || || || || - || - || - || - || - || 1 || - || - || 1 → IF CF || Set Interrupt DisableSEt Carry flag
|-
| STA CLC || 18 (2) || || || 8D (4) || 9D (5) || 99 (5) || || 85 (3) || 95 (4) || || 81 (6) || 91 (6) || || - || - || - || - || - || - || - 0 || A 0 → M CF || Store Accumulator in MemoryCLear Carry flag
|-
| STX SED || F8 (2) || || || 8E (4) || || || || 86 (3) || || 96 (4) || || || || - || - || - || - 1 || - || - || - || X 1 → M DF || Store Index X in MemorySEt Decimal flag
|-
| STY CLD || D8 (2) || || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || - || - || - || - 0 || - || - || - || Y 0 → M DF || Store Index Y in MemoryCLear Decimal flag
|-
| TAX CLV || AA B8 (2) || || || || || || || || || || || || - || N 0 || - || - || - || - || Z || - || A 0 → X VF || Transfer Accumulator to Index XCLear oVerflow flag
|-
| TAY NOP || A8 EA (2) || || || || || || || || || || || || || N - || - || - || - || - || Z || - || A → Y No operation || Transfer Accumulator to Index YNo OPeration
|-
| TSX BPL || BA (2) || || || || || || || || || || || 10 (2+t+p) || || N - || - || - || - || - || Z || - || S → X Branch on NF = 0 || Transfer Stack Pointer to Index XBranch on PLus
|-
| TXA BMI || 8A (2) || || || || || || || || || || || 30 (2+t+p) || || N - || - || - || - || - || Z || - || X → A Branch on NF = 1 || Transfer Index X to AccumulatorBranch on MInus
|-
| TXS BVC || 9A (2) || || || || || || || || || || || || || - 50 (2+t+p) || - || - || - || - || - || - || X → S Branch on VF = 0 || Transfer Index X to Stack PointerBranch on oVerflow Clear
|-
| TYA BVS || 98 || || || || || || || || || || || 70 (2+t+p) || - || - || - || - || - || - || Branch on VF = 1 || Branch on oVerflow Set|-| BCC || || || || N || || || || || || || || 90 (2+t+p) || - || - || - || - || Z - || - || Branch on CF = 0 || Branch on Carry Clear|-| BCS || || || || || || || || || || || || B0 (2+t+p) || - || - || - || - || - || - || Branch on CF = 1 || Branch on Carry Set|-| BNE || || || || || || || || || || || || D0 (2+t+p) || - || - || - || - || - || - || Branch on ZF = 0 || Branch on Not Equal|-| BEQ || || || || || || || || || || || || F0 (2+t+p) || - || - || - || - || - || - || Y → A Branch on ZF = 1 || Transfer Index Y to AccumulatorBranch on EQual
|}
=== Illegal instructions ===
Opcodes in red are unstable. Only 2 A lot of those 7 opcodes ($8Bthese illegal instructions involve a bitwise AND operation, $AB) are actually unstable in the sense that they may produce which is a truly unpredictable resultside effect of the open-drain behavior of NMOS logic. The other 5 opcodes actually produce predictable results – but When two instructions put a value on the conditions under which they do that and bus at the produced results are same time, this creates a bit unexpectedbus conflict resulting effectively in an AND operation. The lower voltage wins because transistors can pull down stronger than resistors can pull up.
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! rowspan=2|Combines !! colspan=10|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description
|-
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! N !! V !! B !! D !! I !! Z !! C
|-
| ANC DCP (ANC2DCM) || AND + ASL/ROL || || 0B, 2B CF (26) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || || D3 (8) || N || - || - || - || - || Z || C || A ∧ M → A- 1 -> M, NF → CF A - M || "AND" Memory with Accumulator then Move Negative Flag to Carry FlagDEC oper + CMP oper
|-
| ARR ISC (ISB, INS) || AND + ROR || || 6B EF (26) || FF (7) || FB (7) || E7 (5) || F7 (6) || || E3 (8) || || F3 (8) || N || V || - || - || - || Z || C || (M + 1 -> M, A ∧ - M) / 2 → - CF -> A || "AND" Accumulator then Rotate RightINC oper + SBC oper
|-
| ASR (ALR) RLA || AND + LSR || || 4B 2F (26) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || 33 (8) || || 0 || - N || - || - || - || Z || C || (M = CF <- [76543210] <- CF, A ∧ AND M) / 2 → -> A || "ROL oper + AND" then Logical Shift Rightoper
|-
| DCP (DCM) RRA || DEC + CMP || || || CF 6F (6) || DF 7F (7) || DB 7B (7) || C7 67 (5) || D7 77 (6) || || C3 63 (8) || D3 73 (8) || N || - || - V || - || - || Z || C || M = CF - 1 → M> [76543210] -> CF, A + M + CF - M > A, CF || Decrement Memory By One then Compare with AccumulatorROR oper + ADC oper
|-
| ISC SLO (ISB, INSASO) || INC + SBC || || || EF 0F (6) || FF 1F (7) || FB 1B (7) || E7 07 (5) || F7 17 (6) || || E3 03 (8) || F3 13 (8) || N || V || - || - || - || Z || C || M + 1 → M= CF <- [76543210] <- 0, A - OR M → -> A || Increment Memory By One then SBC then Subtract Memory from Accumulator with BorrowASL oper + ORA oper
|-
| JAM SRE (KIL, HLTLSE) || || 02, 12, 22,32, 42, 52, 62, 72, 92, B2, D2, F2 || 4F (X6)|| || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || - Z || - C || M = 0 - || > [76543210] - > CF, A EOR M -> A || Stop execution || Halt the CPULSR oper + EOR oper
|-
| LAS (LAR) LAX || STA/TXS + LDA/STX || || |AF (4) | || || BB BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || - || Z || - || M ∧ S → -> A, -> X, S || "AND" Memory with Stack PointerLDA oper + LDX oper
|-
| LAX SAX (LXAAXS, AAX) || LDA + LDX || || style="color: #CC0000;"|'''AB''' (2) || AF 8F (4) || || BF (4+p) || A7 87 (3) || || B7 97 (4) || A3 83 (6) || B3 (5+p) || N - || - || - || - || - || Z || - || M → A, AND X -> M || Load Accumulator Stores the bitwise AND of A and Index Register X From Memory
|-
| NOP LAS (DOP, TOPLAR) || || 1A, 3A, 5A,7A, DA, FA (2)|| 80, 82, 89,C2, E2 (2)|| 0C (4) || 1C, 3C, 5C,7C, DC, FC BB (4+p)|| || 04, 44, 64 (3) || 14, 34, 54,74, D4, F4 (4)|| || || N || - || - || - || - Z || - || M AND SP - > A, X, SP || - || No operation || No OperationLDA/TSX oper
|-
| RLA TAS (XAS, SHS) || ROL + AND || || || 2F (6) || 3F (7) style="color: #CC0000;"|| 3B (7) || 27 '''9B''' (5) || 37 (6) || || 23 (8) || 33 (8) || N || - || - || - || - || Z - || C - || CF ← /M7...M0/ ← CFA AND X -> SP, A ∧ AND X AND (H+1) -> M → A || Rotate Left then "Puts A AND" with AccumulatorX in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| RRA SHA (AHX, AXA) || ROR + ADC || || || 6F (6) || 7F (7) style="color: #CC0000;"|| 7B '''9F''' (75) || 67 (5) || 77 (6) || || 63 (8) || 73 style="color: #CC0000;"|'''93''' (86) || N - || V - || - || - || - || Z || C - || CF → /M7...M0/ → CF, A AND X AND (H+ 1) -> M + CF → A || Rotate Right and Add Memory to AccumulatorStores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SAX SHX (AXSA11, AAXSXA, XAS) || STA + STX || || || 8F (4) || |style="color: #CC0000;"| || 87 '''9E''' (35) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || - || A ∧ X → AND (H+1) -> M || Store Accumulator "AND" Index Register Stores X in MemoryAND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SBC SHY (USBCSYA, SAY) || SBC + NOP || || EB (2) || style="color: #CC0000;"|'''9C''' (5) | || || || || || || |- | N || V - || - || - || - || Z || C - || A Y AND (H+1) - > M - ~CF → A || Subtract Memory from Accumulator with BorrowStores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SBX ANE (AXS, SAXXAA) || CMP + DEX || style="color: #CC0000;"|| CB '''8B''' (2) || || || || || || || || || N || - || - || - || - || Z || C - || (A ∧ XOR magic) - M → AND X AND oper -> A || Subtract Memory from Accumulator "* AND" Index Register X+ AND operhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Turrican 3 on C64 requires a different magic constant than $EE for ANE. $EF is recommended by Groepaz (VICE team)
|-
| SHA LXA (AHX, AXALAX) || STA/STX/STY || || || || || style="color: #CC0000;"|'''9FAB''' (52) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - | N || - || - || - || Z || - || (A ∧ OR magic) AND oper -> A -> X ∧ V → M || Store Accumulator "* AND" Index Register oper in A and X "AND" Valuehighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Wizball on C64 requires a $EE magic constant for LXA
|-
| SHS ALR (TAS, XASASR) || STA/TXS + LDA/TSX || 4B (2) || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || 0 || - || - || - || - Z || - C || A AND oper, 0 - || > [76543210] - > CF || A ∧ X → S, S ∧ (H AND oper + 1) → M || Transfer Accumulator "AND" Index Register X to Stack Pointer then Store Stack Pointer "AND" Hi-Byte In MemoryLSR
|-
| SHX (SXA, XAS) ARR || STA/STX/STY || 6B (2) || || || || style="color: #CC0000;"|'''9E''' (5) || || || || |N | || - V || - || - || - Z || - C || A AND oper, CF - || > [76543210] - > CF || X ∧ (H AND oper + 1) → M || Store Index Register X "AND" ValueROR
|-
| SHY (SYA, SAY) ANC || STA/STX/STY || 0B (2) || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || N || - || - || - || - Z || - C || - || - || Y ∧ A AND oper, bit(H + 17) → M -> CF || Store Index Register Y "AND" Valueoper + set CF as ASL
|-
| SLO (ASO) ANC2 || ASL + ORA || || || 0F 2B (62) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - N || - || - || - || Z || C || M * 2 → MA AND oper, A ∨ M → A bit(7) -> CF || Arithmetic Shift Left then "OR" Memory with AccumulatorAND oper + set CF as ROL
|-
| SRE SBX (LSEAXS, SAX) || LSR + EOR || || || 4F CB (62) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - N || - || - || - || Z || C || M / 2 → M, A ⊻ M → (A AND X) - oper -> X || Logical Shift Right then "Exclusive OR" Memory with AccumulatorCMP and DEX at once, sets flags like CMP
|-
| XAA USBC (ANESBC) || TXA + AND || EB (2) || style="color: #CC0000;"|'''8B''' | || || || || || || || N || V || - || - || Z || C || A - M - ~CF -> A || SBC oper + NOP|-| JAM (2KIL, HLT) || 02, 12, 22,32, 42, 52, 62, 72, 92, B2, D2, F2 (X)|| || || || || || || || || N || - || - || - || - || Z - || - || Stop execution || Halt the CPU. The processor will be trapped infinitely in T1 phase with $FF on the data bus. Reset required.|-| NOP (A ∨ VDOP, TOP) ∧ X ∧ M → A || Non-deterministic Operation of Accumulator1A, Index Register X3A, Memory and Bus Contents5A,7A, DA, FA (2)|| 80, 82, 89,C2, E2 (2)|| 0C (4) || 1C, 3C, 5C,7C, DC, FC (4+p)|| || 04, 44, 64 (3) || 14, 34, 54,74, D4, F4 (4)|| || || || - || - || - || - || - || - || No operation || No Operation
|}
Opcodes in red are unstable.
<br>
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 00 || BRK
|-
| 04 xx || '''NOP ''zpg'''''
|-
| 08 || PHP
|-
| 0C xx xx || '''NOP ''abs'''''
|-
| 10 xx || BPL ''rel''
|-
| 14 xx || '''NOP ''zpg'',X'''
|-
| 18 || CLC
|-
| 1C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 20 xx xx || JSR ''abs''
|-
| 24 xx || BIT ''zpg''
|-
| 28 || PLP
|-
| 2C xx xx || BIT ''abs''
|-
| 30 xx || BMI ''rel''
|-
| 34 xx || '''NOP ''zpg'',X'''
|-
| 38 || SEC
|-
| 3C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 40 || RTI
|-
| 44 xx || '''NOP ''zpg'''''
|-
| 48 || PHA
|-
| 4C xx xx || JMP ''abs''
|-
| 50 xx || BVC ''rel''
|-
| 54 xx || '''NOP ''zpg'',X'''
|-
| 58 || CLI
|-
| 5C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 60 || RTS
|-
| 64 xx || '''NOP ''zpg'''''
|-
| 68 || PLA
|-
| 6C xx xx || JMP ''zpgind''
|-
| 70 xx || BVS ''rel''
|-
| 74 xx || '''NOP ''zpg'',X'''
|-
| 78 || SEI
|-
| 7C xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 80 xx || '''NOP #'''
|-
| 84 xx || STY ''zpg''
|-
| 88 || DEY
|-
| 8C xx xx || STY ''abs''
|-
| 90 xx || BCC ''rel''
|-
| 94 xx || STY ''zpg'',X
|-
| 98 || TYA
|-
| 9C xx xx ||style="color: #CC0000;"|'''SHY ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A0 xx || LDY #
|-
| A4 xx || LDY ''zpg''
|-
| A8 || TAY
|-
| AC xx xx || LDY ''abs''
|-
| B0 xx || BCS ''rel''
|-
| B4 xx || LDY ''zpg'',X
|-
| B8 || CLV
|-
| BC xx xx || LDY ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C0 xx || CPY #
|-
| C4 xx || CPY ''zpg''
|-
| C8 || INY
|-
| CC xx xx || CPY ''abs''
|-
| D0 xx || BNE ''rel''
|-
| D4 xx || '''NOP ''zpg'',X'''
|-
| D8 || CLD
|-
| DC xx xx || '''NOP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E0 xx || CPX #
|-
| E4 xx || CPX ''zpg''
|-
| E8 || INX
|-
| EC xx xx || CPX ''abs''
|-
| F0 xx || BEQ ''rel''
|-
| F4 xx || '''NOP ''zpg'',X'''
|-
| F8 || SED
|-
| FC xx xx || '''NOP ''abs'',X'''
|}
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 01 xx || ORA (''zpg'',X)
|-
| 05 xx || ORA ''zpg''
|-
| 09 xx || ORA #
|-
| 0D xx xx || ORA ''abs''
|-
| 11 xx || ORA (''zpg''),Y
|-
| 15 xx || ORA ''zpg'',X
|-
| 19 xx xx || ORA ''abs'',Y
|-
| 1D xx xx || ORA ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 21 xx || AND (''zpg'',X)
|-
| 25 xx || AND ''zpg''
|-
| 29 xx || AND #
|-
| 2D xx xx || AND ''abs''
|-
| 31 xx || AND (''zpg''),Y
|-
| 35 xx || AND ''zpg'',X
|-
| 39 xx xx || AND ''abs'',Y
|-
| 3D xx xx || AND ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 41 xx || EOR (''zpg'',X)
|-
| 45 xx || EOR ''zpg''
|-
| 49 xx || EOR #
|-
| 4D xx xx || EOR ''abs''
|-
| 51 xx || EOR (''zpg''),Y
|-
| 55 xx || EOR ''zpg'',X
|-
| 59 xx xx || EOR ''abs'',Y
|-
| 5D xx xx || EOR ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 61 xx || ADC (''zpg'',X)
|-
| 65 xx || ADC ''zpg''
|-
| 69 xx || ADC #
|-
| 6D xx xx || ADC ''abs''
|-
| 71 xx || ADC (''zpg''),Y
|-
| 75 xx || ADC ''zpg'',X
|-
| 79 xx xx || ADC ''abs'',Y
|-
| 7D xx xx || ADC ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 81 xx || STA (''zpg'',X)
|-
| 85 xx || STA ''zpg''
|-
| 89 xx || '''NOP #'''
|-
| 8D xx xx || STA ''abs''
|-
| 91 xx || STA (''zpg''),Y
|-
| 95 xx || STA ''zpg'',X
|-
| 99 xx xx || STA ''abs'',Y
|-
| 9D xx xx || STA ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A1 xx || LDA (''zpg'',X)
|-
| A5 xx || LDA ''zpg''
|-
| A9 xx || LDA #
|-
| AD xx xx || LDA ''abs''
|-
| B1 xx || LDA (''zpg''),Y
|-
| B5 xx || LDA ''zpg'',X
|-
| B9 xx xx || LDA ''abs'',Y
|-
| BD xx xx || LDA ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C1 xx || CMP (''zpg'',X)
|-
| C5 xx || CMP ''zpg''
|-
| C9 xx || CMP #
|-
| CD xx xx || CMP ''abs''
|-
| D1 xx || CMP (''zpg''),Y
|-
| D5 xx || CMP ''zpg'',X
|-
| D9 xx xx|| CMP ''abs'',Y
|-
| DD xx xx || CMP ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E1 xx || SBC (''zpg'',X)
|-
| E5 xx || SBC ''zpg''
|-
| E9 xx || SBC #
|-
| ED xx xx || SBC ''abs''
|-
| F1 xx || SBC (''zpg''),Y
|-
| F5 xx || SBC ''zpg'',X
|-
| F9 xx xx || SBC ''abs'',Y
|-
| FD xx xx || SBC ''abs'',X
|}
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 02 || '''JAM'''
|-
| 06 xx || ASL ''zpg''
|-
| 0A || ASL A
|-
| 0E xx xx || ASL ''abs''
|-
| 12 || '''JAM'''
|-
| 16 xx || ASL ''zpg'',X
|-
| 1A || '''NOP'''
|-
| 1E xx xx || ASL ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 22 || '''JAM'''
|-
| 26 xx || ROL ''zpg''
|-
| 2A || ROL A
|-
| 2E xx xx || ROL ''abs''
|-
| 32 || '''JAM'''
|-
| 36 xx || ROL ''zpg'',X
|-
| 3A || '''NOP'''
|-
| 3E xx xx || ROL ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 42 || '''JAM'''
|-
| 46 xx || LSR ''zpg''
|-
| 4A || LSR A
|-
| 4E xx xx || LSR ''abs''
|-
| 52 || '''JAM'''
|-
| 56 xx || LSR ''zpg'',X
|-
| 5A || '''NOP'''
|-
| 5E xx xx || LSR ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 62 || '''JAM'''
|-
| 66 xx || ROR ''zpg''
|-
| 6A || ROR A
|-
| 6E xx xx || ROR ''abs''
|-
| 72 || '''JAM'''
|-
| 76 xx || ROR ''zpg'',X
|-
| 7A || '''NOP'''
|-
| 7E xx xx || ROR ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 82 xx || '''NOP #'''
|-
| 86 xx || STX ''zpg''
|-
| 8A || TXA
|-
| 8E xx xx || STX ''abs''
|-
| 92 || '''JAM'''
|-
| 96 xx || STX ''zpg'',Y
|-
| 9A || TXS
|-
| 9E xx xx ||style="color: #CC0000;"|'''SHX ''abs'',Y'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A2 xx || LDX #
|-
| A6 xx || LDX ''zpg''
|-
| AA || TAX
|-
| AE xx xx || LDX ''abs''
|-
| B2 || '''JAM'''
|-
| B6 xx || LDX ''zpg'',Y
|-
| BA || TSX
|-
| BE xx xx || LDX ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C2 xx || '''NOP #'''
|-
| C6 xx || DEC ''zpg''
|-
| CA || DEX
|-
| CE xx xx || DEC ''abs''
|-
| D2 || '''JAM'''
|-
| D6 xx || DEC ''zpg'',X
|-
| DA || '''NOP'''
|-
| DE xx xx || DEC ''abs'',X
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E2 xx || '''NOP #'''
|-
| E6 xx || INC ''zpg''
|-
| EA || NOP
|-
| EE xx xx || INC ''abs''
|-
| F2 || '''JAM'''
|-
| F6 xx || INC ''zpg'',X
|-
| FA || '''NOP'''
|-
| FE xx xx || INC ''abs'',X
|}
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 03 xx || '''SLO (''zpg'',X)'''
|-
| 07 xx || '''SLO ''zpg'''''
|-
| 0B xx || '''ANC #'''
|-
| 0F xx xx || '''SLO ''abs'''''
|-
| 13 xx || '''SLO (''zpg''),Y'''
|-
| 17 xx || '''SLO ''zpg'',X'''
|-
| 1B xx xx || '''SLO ''abs'',Y'''
|-
| 1F xx xx || '''SLO ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 23 xx || '''RLA (''zpg'',X)'''
|-
| 27 xx || '''RLA ''zpg'''''
|-
| 2B xx || '''ANC #'''
|-
| 2F xx xx || '''RLA ''abs'''''
|-
| 33 xx || '''RLA (''zpg''),Y'''
|-
| 37 xx || '''RLA ''zpg'',X'''
|-
| 3B xx xx || '''RLA ''abs'',Y'''
|-
| 3F xx xx || '''RLA ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 43 xx || '''SRE (''zpg'',X)'''
|-
| 47 xx || '''SRE ''zpg'''''
|-
| 4B xx || '''ASR #'''
|-
| 4F xx xx || '''SRE ''abs'''''
|-
| 53 xx || '''SRE (''zpg''),Y'''
|-
| 57 xx || '''SRE ''zpg'',X'''
|-
| 5B xx xx || '''SRE ''abs'',Y'''
|-
| 5F xx xx|| '''SRE ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 63 xx || '''RRA (''zpg'',X)'''
|-
| 67 xx || '''RRA ''zpg'''''
|-
| 6B xx || '''ARR #'''
|-
| 6F xx xx || '''RRA ''abs'''''
|-
| 73 xx || '''RRA (''zpg''),Y'''
|-
| 77 xx || '''RRA ''zpg'',X'''
|-
| 7B xx xx || '''RRA ''abs'',Y'''
|-
| 7F xx xx || '''RRA ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| 83 xx || '''SAX (''zpg'',X)'''
|-
| 87 xx || '''SAX ''zpg'''''
|-
| 8B xx ||style="color: #CC0000;"|'''XAA ANE #'''
|-
| 8F xx xx || '''SAX ''abs'''''
|-
| 93 xx ||style="color: #CC0000;"|'''SHA (''zpg''),Y'''
|-
| 97 xx || '''SAX ''zpg'',Y'''
|-
| 9B xx xx ||style="color: #CC0000;"|'''SHS TAS ''abs'',Y'''
|-
| 9F xx xx ||style="color: #CC0000;"|'''SHA ''abs'',Y'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| A3 xx || '''LAX (''zpg'',X)'''
|-
| A7 xx || '''LAX ''zpg'''''
|-
| AB xx ||style="color: #CC0000;"|'''LXA #'''
|-
| AF xx xx || '''LAX ''abs'''''
|-
| B3 xx || '''LAX (''zpg''),Y'''
|-
| B7 xx || '''LAX ''zpg'',Y'''
|-
| BB xx xx || '''LAS ''abs'',Y'''
|-
| BF xx xx || '''LAX ''abs'',Y'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| C3 xx || '''DCP (''zpg'',X)'''
|-
| C7 xx || '''DCP ''zpg'''''
|-
| CB xx || '''SBX #'''
|-
| CF xx xx || '''DCP ''abs'''''
|-
| D3 xx || '''DCP (''zpg''),Y'''
|-
| D7 xx || '''DCP ''zpg'',X'''
|-
| DB xx xx || '''DCP ''abs'',Y'''
|-
| DF xx xx || '''DCP ''abs'',X'''
|}
|
{| class="wikitable"
! Opc Opcode !! Mnemonic
|-
| E3 xx || '''ISC (''zpg'',X)'''
|-
| E7 xx || '''ISC ''zpg'''''
|-
| EB xx || '''SBC USBC #'''
|-
| EF xx xx || '''ISC ''abs'''''
|-
| F3 xx || '''ISC (''zpg''),Y'''
|-
| F7 xx || '''ISC ''zpg'',X'''
|-
| FB xx xx || '''ISC ''abs'',Y'''
|-
| FF xx xx || '''ISC ''abs'',X'''
|}
|}
Opcodes in bold are illegal. Opcodes in red are unstable.
Any instruction xxxxxx11 will execute the instructions at xxxxxx01 and xxxxxx10 at once, using the address mode of the instruction at xxxxxx01.
For example, "SAX abs” ($8F) is the composite of “STA abs” ($8D) and “STX abs” ($8E).
<br>
* On NMOS, an indirect JMP will behave unexpectedly when the indirect address crosses a page boundary, because the 6502 does not add the carry to calculate the address of the high byte. For example, JMP ($19FF) will use the contents of $19FF and $1900 for the JMP address. On CMOS, this issue was fixed, at the cost of 1 additional cycle. In our example, JMP ($19FF) will use the contents of $19FF and $2000 for the JMP address.
* Some instructions, particularly those involving branches or indexed addressing modes, incur an extra cycle if the processor has to cross a memory page boundary. This is problematic for time-sensitive code.
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The TXS instruction does not affect any flag, while all other transfer instructions do.
* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.
* The CLV (Clear Overflow Flag) instruction exist, but not the SEV (Set Overflow Flag) instruction.
* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.
* The alternate NOPs are not created equal. Some have one- or two-byte operands (which they don't do anything with), and they take different amounts of time to execute.
* The CLV (Clear Overflow Flag) instruction exist but not the SEV (Set Overflow Flag) instruction.<br>
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.== Compared behaviour ==
* The alternate NOPs are not created equal6502’s Decimal (BCD) mode automatically adjusts ADC and SBC results, while the Z80 requires a DAA instruction after each BCD addition and subtraction. Some have * The 6502 uses only one- or addressing mode per instruction, while the Z80 can combine twodifferent addressing modes within a single instruction.* The 6502 post-byte operands (which they dondecrements on PHA and pre-increments on PLA, while the Z80 pre-decrements on PUSH and post-increments on POP.* The 6502 saves flags automatically during interrupts; while the Z80 requires PUSH AF and POP AF.* The 6502 only updates flags that are directly relevant to the operation's result. For example, EOR doesn't do anything with)conceptually involve a carry, and they take different amounts of time so the Carry flag is left untouched. On the Z80, XOR always clears the Carry flag to executeensure a clean flag state.
<br>
For a specific example, the 6502 PLA decodes instructions matching 100XX1XX to the control line STY (ignoring the timing bits for simplicity). This takes 1 row in the PLA, but it would take 16 entries in a ROM. [https://news.ycombinator.com/item?id=13128074 Source]
See: [https://web.archive.org/web/20210519010632/http://visual6502.org/wiki/index.php?title=6507_Decode_ROM 6507 Decode ROM (PLA)] [https://pastraiser.com/cpu/65CE02/65CE02_rom.html 65CE02 Decode ROM (PLA)] [https://www.righto.com/2016/02/reverse-engineering-arm1-instruction.html ARM1, Z80, 6502 instruction sequencing compared] [https://www.pagetable.com/?p=410 Internals of BRK/IRQ/NMI/RESET on a MOS 6502] [https://www.pagetable.com/?p=39 How MOS 6502 illegal opcodes really work] [https://c74project.com/wp-content/uploads/2020/04/c74-6502-microcode.pdf 6502 microcode] [https://c74project.com/wp-content/uploads/2020/04/c74-6502-microinstructions.pdf 6502 microinstructions]
<br>
* The ROR instruction didn't exist in the very earliest (pre-1977) chips. See: [https://www.pagetable.com/?p=406 Measuring the ROR Bug in the Early MOS 6502]
* The 6502 core used inside the [[NES]] is missing the Decimal Mode feature. [https://archive.org/details/nes-programmers-reference-guide-by-electronic-arts-1989/ NES programmer's reference guide] [https://www.nesdev.org/NESDoc.pdf NESDoc] [https://www.nesdev.org/wiki/Mapper NES mappers] [https://problemkaputt.de/everynes.htm Noca$h's Everynes] [https://www.nesdev.org/wiki/Emulator_tests NES emulator tests] [https://tcrf.net/Category:Nintendo_Console_Testing_Software Official Nintendo testing software]
* The 6507 CPU, used in the [[Atari VCS]], has only 13 address lines. So it can only address 8KB instead of 64KB. It also lacks the IRQ and NMI interrupt lines. [https://youtu.be/qvpwf50a48E Atari VCS: The Ultimate Talk] [https://cdn.hackaday.io/files/1646277043401568/stella.pdf Stella programmer's guide] [https://www.atarimania.com/documents/stella_system_training_manual.pdf Stella system training manual] [https://problemkaputt.de/2k6specs.htm Noca$h's 2k6specs]
* The 6510 CPU, used in the [[Commodore 64]], is a 6502 with an additional AEC pin that puts the bus in high impedance mode. It also includes a 6-bit I/O port that occupies addresses 0 and 1.
* The 6502C used in [[Atari 8-bit]] computer range, adds an additional HALT pin for DMA. The 6502C is otherwise a regular NMOS 6502, not to be confused with the CMOS 65C02.
* The CMOS 65C02 fixed multiple bugs of the original NMOS 6502, but also removed access to all illegal instructions. Some cycle counts have been modified and some extra instructions have been added. In fact, there are multiple implementations of the 65C02 (WDC 65C02, WDC 65C02S, Rockwell R65C02, CSG 65CE02, ...), each with its own variant of the instruction set[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference].
* The HuC6280, used in the [[PC-Engine]] gaming console, is an improved version of the CMOS 65C02. [[mediaMedia:HuC6280 - CMOS 8-bit Microprocessor Hardware Manual.pdf|HuC6280 hardware manual]] [[Media:HuC6260 - CMOS Video Color Encoder Manual.pdf|HuC6260 VCE manual]] [[Media:HuC6270 - CMOS Video Display Controller Manual.pdf|HuC6270 VDC manual]]
* The WDC 65C816, used in the [[SNES]] and the [[Apple IIGS]], is a 16-bit version of the 65C02 [https://wwwarchive.westerndesigncenter.comorg/wdcdetails/documentationSNESDevManual/w65c816sSNES development manual] [https://problemkaputt.pdf 65C816 datasheetde/fullsnes.htm Noca$h's fullsnes] [https://archivesnes.nesdev.org/detailswiki/SNESDevManual/ SNES development manualSNESdev_Wiki SNESdev wiki]. It The 65C816 contains a compatibillity mode, enabled by default upon reset, that makes it behave like a regular 65C02. The full 65C816 cycle-by-cycle steps are in the [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet].
* The Sony SPC700 sound CPU used inside the SNES also behaves similarly to a 6502 with some extensions. [https://wiki.superfamicom.org/spc700-reference Source] [https://www.youtube.com/watch?v=zrn0QavLMyo&list=PLHQ0utQyFw5JD2wWda50J8XuzQ2cFr8RX SPC700 Series] [https://github.com/gilyon/snes-tests SNES-tests]
<br>
*[http://www.6502.org/ 6502.org] the 6502 microprocessor resource
*[[Media:Onthe6502.pdf|On the 6502 - A brillant or sloppy design?]]
*[https://youtu.be/acUH4lWe2NQ The 6502 CPU Powered a Whole Generation!] by [[The 8-Bit Guy]]
*[https://youtu.be/Ne1ApyqSvm0 Oral history of Bill Mensch]
*[https://www.chibiakumas.com/6502/ Learn Assembly Programming with ChibiAkumas] Multi-platform 6502 tutorial
*[https://www.nesdev.org/obelisk-6502-guide/ Obelisk 6502 Guide]
*[https://www.masswerk.at/6502/6502_instruction_set.html 6502 Instruction Set]*[https://www.pagetablemasswerk.comat/c64refnowgobang/65022021/?tab=2 6502 Family CPU Reference-illegal-opcodes 6502 illegal opcodes demystified]*[[Media:NoMoreSecrets-NMOS6510UnintendedOpcodes-20212412.pdf|No more secrets - NMOS 6510 Unintended Opcodes]]
*[https://llx.com/Neil/a2/opcodes.html The 6502/65C02/65C816 Instruction Set Decoded]
*[https://pastraiser.com/cpu/6502/6502_opcodes.html 6502 opcodes] [https://pastraiser.com/cpu/65CE02/65CE02_opcodes.html 65CE02 opcodes]
*[https://www.nesdev.org/wiki/CPU_unofficial_opcodes Opcode matrix arrangement]
*[https://www.oxyron.de/html/opcodes02opcodes.html Oxyron Opcode MatrixMatrices]*[http://retro.hansotten.nl/uploads/books/Programming_the_6502.pdf Rodnay Zaks Programming the 6502]
*[http://www.6502.org/documents/datasheets/synertek/synertek_programming_manual.pdf Synertek SY650x programming manual (250 pages)]
*[http://www.6502.org/documents/datasheets/synertek/synertek_hardware_manual.pdf Synertek SY650x hardware manual (178 pages)]
*[[Media:SY6500 - SY65C02 datasheet.pdf]] - provides features a detailed breakdown of the machine cycles65C02 instructions*[https://xotmatrix.github.io/6502/ xotmatrix] 6502 instruction set and detailed cycle-by-cycle breakdown
*[[Media:6502 (65xx) Microprocessor Instant Reference Card.pdf]]
*[https://www.nesdev.org/wiki/CPU_interrupts 6502 Interrupts]
*[[Media:6502-dead-cycles.pdf]]
*[https://codebase64.org/doku.php?id=base:6510_instruction_timing 6510 Instruction Timing]
*[[Media:NoMoreSecrets-NMOS6510UnintendedOpcodes-20212412.pdf|No more secrets - NMOS 6510 Unintended Opcodes]]
*[https://youtu.be/fWqBmmPQP40 Conference - Reverse Engineering the MOS 6502 CPU]
*[https://floooh.github.io/visual6502remix/ Visual6502remix] [https://www.nesdev.org/wiki/Visual6502wiki Visual6502wiki]
*[https://c74project.com/ C74-6502] [https://monster6502.com/ MOnSter 6502] Dis-integrated implementations of the 6502 microprocessor
*[https://hackaday.io/project/21496/logs FPGA NES] [https://floooh.github.io/visual2a03remix/ Visual2A03remix] [https://github.com/emu-russia/breaks/tree/master/BreakingNESWiki_DeepL Breaking NES wiki]
*[https://www.maizure.org/projects/decoded-bisqwit-nes-emulator/ Decoded: The Bisqwit NES Emulatoremulator] [https://bugzmanov.github.io/nes_ebook/ Writing NES emulator in Rust] [https://emudev.de/ Emudev (nes-c64-snes)]
*[https://floooh.github.io/2019/12/13/cycle-stepped-6502.html Cycle-stepped 6502 emulation how-to]
*[https://github.com/SingleStepTests Tom Harte's SingleStepTests]