<br>
== Registers Register File ==
{| class="wikitable" style="white-space: nowrap;"
* bit0 - CF - Carry Flag: 1 on unsigned overflow
|| Flags are affected by most operations.
The BF is bit does not a physical flag implemented in a registeractually exist inside the 6502. It The BF bit only appears on exists in the status flag byte pushed to the stack when . When the P register flags are restored (via PLP or RTI), the BF bit is pushed to itdiscarded.
PHP (Push Processor Status) and PLP (Pull Processor Status) can be used to set or retrieve P directly via the stack.
|}
SeeThe 6502 also has internal latches and buffers used for address handling and instruction execution. For example: [https*ABL/ABH:Address Bus Low//www.rightoHigh, latches for the address bus.com/2012/12*AI/BI: Input Registers for the-6502-overflow-flag-explainedALU.*IR: Instruction Register, holds the fetched instruction opcode byte while the CPU decodes and executes it.html The 6502 overflow flag explained mathematically]
<br>
== Decimal Mode ==
The 6502’s Decimal (BCD) mode automatically adjusts Mode allows ADC and SBC resultsinstructions to use Binary-Coded Decimal (BCD), while the Z80 requires a DAA instruction after where each BCD addition and subtractionnibble (4 bits) represents a decimal digit (0-9), instead of binary.
On NMOS, when Decimal Mode is on, the ADC and SBC instructions update NF, VF and ZF based on the binary result before the decimal correction is applied. Only CF is updated correctly. On CMOS, all the flags are updated correctly, at the cost of 1 additional cycle.
== Pipelining ==
The 6502 CPU uses some sort We have to dispel the myth of pipeliningin the 6502. If an instruction does not store data we analyze its operation in memory on its last cyclehalf-cycles, the processor can fetch the opcode of the next we see that instruction while executing the last cycle. This execution is very primitive as the 6502 does not have an instruction cache nor even a prefetch queue. It relies on RAM tightly bound to hold all program informationmemory operations without any overlap between different instructions.
As an exampleEach instruction follows a rigid sequence of steps, with no ability to fetch the next instruction EOR #$FF truly takes 3 cycles:* On while executing the first cycle, current one. This means that the opcode $49 will be fetched* During the second cycle the processor decodes the opcode and fetches the parameter #$FF* On the third cycle, the processor will perform the operation and store the result CPU cannot prefetch opcodes or operands ahead of time in register A, but simultaneously it fetches the opcode for the next instructionway a pipelined architecture would.
This is If we invert our perspective and consider ϕ2 as the first half-cycle and ϕ1 as the second, it becomes evident why pipelining does not exist on the EOR instruction effectively takes only 2 cycles6502.
However, this pipelining only makes sense when looking at full cycles. If we break it down into half-cycles, there's no actual overlap. In fact, it's the other way around. If the previous instruction ends with a memory write, the CPU has to wait for a half-cycle before fetching being able to fetch the next instruction on the next ϕ2 half-cycle.
<br>
== Adressing Modes ==
The 6502 uses only one addressing mode per instruction.
{| class="wikitable"
The Zero Page on the 6502 is a special area of memory from addresses $0000 to $00FF that act like pseudo registers. The 6502 provides optimized instructions that operate more efficiently when using addresses within the Zero Page.
Fun fact: the TMS9900 CPU took this further, and had by having no onboard registers (other than , except PC & status register). Everything was in RAM.
<br>
#Operand Fetch (if needed)
#Memory Read / I/O Read (if needed)
#ExecutionOperation
#Memory Write / I/O Write (if needed)
#At the end of every instruction, the IRQ (if the interrupt disable flag is clear) and NMI pins are checked.
As an example, let M[$42]=$80, M[$43]=$10 and Y=$F1. Then the instruction LDA ($42),Y will execute as follow, with ϕ2 as the first half-cycle and ϕ1 as the second half-cycle:
*T0: Fetch opcode $B1 (LDA (zp),Y) from memory then increment PC
*T1: Fetch operand byte $42 (zero page pointer address) then increment PC
*T2: Get low byte from zero page ($80) then increment the zero page address
*T3: Get high byte from next zero page location ($10) then add the Y register value ($F1) to $1080
*T4: Garbage fetch from memory address $1071 then handle page boundary crossing (since $1080 + $F1 crosses a page)
*T5: Read the value from memory address $1171 into the accumulator then no operation in the last half-cycle
<br>
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! colspan=13|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description
|-
! ''No arg'' !! A !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C
|-
| ADC BIT || || || 69 (2) || 6D 2C (4) || 7D (4+p) || 79 (4+p) || || 65 24 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || - || Z || C - || A + ∧ M + CF , M<sub>7</sub> → ANF, CF M<sub>6</sub> → VF || ADd with Carrytest BITs
|-
| AND || || || 29 (2) || 2D (4) || 3D (4+p) || 39 (4+p) || || 25 (3) || 35 (4) || || 21 (6) || 31 (5+p) || || N || - || - || - || - || Z || - || A ∧ M → A || bitwise AND with accumulator
|-
| ASL EOR || || 0A || 49 (2) || 4D (4) || 0E 5D (64+p) || 1E 59 (74+p) || || || 06 45 (53) || 16 55 (64) || || 41 (6) || 51 (5+p) || || N || - || - || - || - || Z || C - || CF ← /M<sub>7</sub>...A ⊻ M<sub>0</sub>/ ← 0 → A || Arithmetic Shift Leftbitwise Exclusive OR
|-
| CMP ORA || || || C9 09 (2) || CD 0D (4) || DD 1D (4+p) || D9 19 (4+p) || || C5 05 (3) || D5 15 (4) || || C1 01 (6) || D1 11 (5+p) || || N || - || - || - || - || Z || C - || A - ∨ M → A || CoMPare accumulatorbitwise OR with Accumulator
|-
| CPX ADC || || || E0 69 (2) || EC 6D (4) || 7D (4+p) || 79 (4+p) || || E4 65 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || - || - V || - || - || Z || C || X - A + M + CF → A, CF || ComPare X registerADd with Carry
|-
| CPY SBC || || || C0 E9 (2) || CC ED (4) || FD (4+p) || F9 (4+p) || || C4 E5 (3) || F5 (4) || || E1 (6) || F1 (5+p) || || N || - || - V || - || - || Z || C || Y A - M - (1 - CF) → A || ComPare Y registerSuBtract with Carry
|-
| DEC CMP || || || C9 (2) || CE CD (64) || DE DD (74+p) || D9 (4+p) || || C6 C5 (53) || D6 D5 (64) || || C1 (6) || D1 (5+p) || || N || - || - || - || - || Z || - C || M A - 1 → M || DECrement memoryCoMPare accumulator
|-
| DEX CPX || CA (2) || || E0 (2) || EC (4) || || || || E4 (3) || || || || || || N || - || - || - || - || Z || - C || X - 1 → X M || DEcrement ComPare Xregister
|-
| DEY CPY || 88 (2) || || C0 (2) || CC (4) || || || || C4 (3) || || || || || || N || - || - || - || - || Z || - C || Y - 1 → Y M || DEcrement ComPare Yregister
|-
| EOR ASL || || || 49 0A (2) || 4D (4) || 5D 0E (4+p6) || 59 1E (4+p7) || || 45 || 06 (35) || 55 16 (46) || || 41 (6) || 51 (5+p) || || N || - || - || - || - || Z || - C || A ⊻ CF ← /M<sub>7</sub>...M → A <sub>0</sub>/ ← 0 || bitwise Exclusive ORArithmetic Shift Left
|-
| INC LSR || || 4A (2) || || EE 4E (6) || FE 5E (7) || || || E6 46 (5) || F6 56 (6) || || || || || N || - 0 || - || - || - || Z || - C || M + 1 0 → /M <sub>7</sub>...M<sub>0</sub>/ → CF || INCrement memoryLogical Shift Right
|-
| INX ROL || E8 || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || || 36 (6) || || || || || N || - || - || - || - || Z || - C || X + 1 → X CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← CF || INcrement XROtate Left
|-
| INY ROR || C8 || 6A (2) || || 6E (6) || 7E (7) || || || 66 (5) || || 76 (6) || || || || || N || - || - || - || - || Z || - C || Y + 1 CF → /M<sub>7</sub>...M<sub>0</sub>/ → Y CF || INcrement YROtate Right
|-
| LSR DEC || || 4A (2) || || 4E CE (6) || 5E DE (7) || || || 46 C6 (5) || 56 D6 (6) || || || || || 0 || - N || - || - || - || Z || C - || 0 → /M<sub>7</sub>...M<sub>0</sub>/ - 1 → CF M || Logical Shift RightDECrement memory
|-
| ORA INC || || || 09 (2) || 0D EE (46) || 1D FE (4+p7) || 19 (4+p) || || 05 E6 (35) || 15 F6 (46) || || 01 (6) || 11 (5+p) || || N || - || - || - || - || Z || - || A ∨ M + 1 → A M || bitwise OR with AccumulatorINCrement memory
|-
| ROL DEX || || 2A CA (2) || || 2E (6) || 3E (7) || || || 26 (5) || 36 (6) || || || || || N || - N || - || - || - || Z || C - || CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← CF X - 1 → X || ROtate LeftDEcrement X
|-
| ROR DEY || || 6A 88 (2) || || 6E (6) || 7E (7) || || || 66 (5) || 76 (6) || || || || || N || - N || - || - || - || Z || C - || CF → /M<sub>7</sub>...M<sub>0</sub>/ Y - 1 → CF Y || ROtate RightDEcrement Y
|-
| SBC INX || E8 (2) || || E9 (2) || ED (4) || FD (4+p) || F9 (4|| || || || || || || || N || - || - || - || Z || - || X +p) 1 → X || INcrement X|-| E5 (3) INY || F5 C8 (42) || || E1 (6) || F1 (5+p) || || N || V || || || || || || || N || - || - || - || Z || C - || A - M - (Y + 1 - CF) → A Y || SuBtract with CarryINcrement Y
|}
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! colspan=12|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description
|-
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C
|-
| LDA || || A9 (2) || AD (4) || BD (4+p) || B9 (4+p) || || A5 (3) || B5 (4) || || A1 (6) || B1 (5+p) || || N || - || - || - || - || Z || - || M → A || LoaD Accumulator
|-
| LDX || || A2 (2) || AE (4) || || BE (4+p) || || A6 (3) || || B6 (4) || || || || N || - || - || - || - || Z || - || M → X || LoaD X register
|-
| LDY || || A0 (2) || AC (4) || BC (4+p) || || || A4 (3) || B4 (4) || || || || || N || - || - || - || - || Z || - || M → Y || LoaD Y register
|-
| PHA STA || 48 (3) || || 8D (4) || 9D (5) || 99 (5) || || 85 (3) || 95 (4) || || 81 (6) || 91 (6) || || - || - || - || - || - || - || - || A↓ A → M || PusH STore Accumulator
|-
| PHP STX || 08 (3) || || 8E (4) || || || || 86 (3) || || 96 (4) || || || || - || - || 1 || - || - || - || - || P↓ X → M || PusH Processor statusSTore X register
|-
| PLA STY || 68 (4) || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || N - || - || - || - || - || Z || - || (S)↑ Y → A M || PuLl AccumulatorSTore Y register
|-
| PLP TAX || 28 AA (42) || || || || || || || || || || || || N || V - || - || D || I - || Z || C - || (S)↑ A → P X || PuLl Processor statusTransfer A to X
|-
| STA TXA || 8A (2) || || 8D (4) || 9D (5) || 99 (5) || || 85 (3) || 95 (4) || || 81 (6) || 91 (6) || || - N || - || - || - || - Z || - || - X → A || Transfer X to A → M || STore Accumulator
|-
| STX TAY || A8 (2) || || 8E (4) || || || || 86 (3) || || 96 (4) || || || || - N || - || - || - || - || - Z || - || X A → M Y || STore X registerTransfer A to Y
|-
| STY TYA || 98 (2) || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || - N || - || - || - || - || - Z || - || Y → M A || STore Transfer Y registerto A
|-
| TAX TSX || AA BA (2) || || || || || || || || || || || || N || - || - || - || - || Z || - || A S → X || Transfer A Stack pointer to X
|-
| TAY TXS || A8 9A (2) || || || || || || || || || || || || N - || - || - || - || - || Z || - || A X → Y S || Transfer A X to YStack pointer
|-
| TSX PLP || BA 28 (24) || || || || || || || || || || || || N || - V || - D || - || - I || Z || - C || (S )↑ → X P || Transfer Stack pointer to XPuLl Processor status
|-
| TXA PLA || 8A 68 (24) || || || || || || || || || || || || N || - || - || - || - || Z || - || X (S)↑ → A || Transfer X to APuLl Accumulator
|-
| TXS PHP || 9A 08 (23) || || || || || || || || || || || || - || - || - || - || - || - || - || X → S P↓ || Transfer X to Stack pointerPusH Processor status
|-
| TYA PHA || 98 48 (23) || || || || || || || || || || || || N - || - || - || - || - || Z || - || Y → A A↓ || Transfer Y to APusH Accumulator
|}
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! colspan=12|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description|-! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! B !! D !! I !! Z !! C
|-
| BCC || || || || || || || || || || || || 90 ! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! (2+t+p$nnnn) || - || - || - || - || - || - || - || Branch on CF = 0 || Branch on Carry Clear!! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! D !! I !! Z !! C
|-
| BCS JMP || || || 4C (3) || || || 6C (5) || || || || || || B0 (2+t+p) || - || - || - || - || - || - || - || Branch on CF = [PC + 1 ] → PCL, [PC + 2] → PCH || Branch on Carry SetJuMP
|-
| BEQ JSR || || || 20 (6) || || || || || || || || || F0 (2+t+p) || - || - || - || - || - || - || - || Branch on ZF = PC + 2↓, [PC + 1 ] → PCL, [PC + 2] → PCH || Branch on EQualJump to SubRoutine
|-
| BIT RTS || || || 2C 60 (46) || || || || 24 (3) || || || || || || N || V || - || - || - || Z - || - || A ∧ M- || (S)↑ → PCL, M<sub>7</sub> (S)↑ → NFPCH, M<sub>6</sub> PC + 1 → VF PC || test BITsReTurn from Subroutine
|-
| BMI RTI || 40 (6) || || || || || || || || || || || 30 (2+t+p) || - N || - V || - D || - I || - Z || - C || - || Branch on NF = 1 (S)↑ → P, (S)↑ → PCL, (S)↑ → PCH || Branch on MInusReTurn from Interrupt
|-
| BNE BRK || 00 (7) || || || || || || || || || || || D0 (2+t+p) || - || - || - || - 1 || - || - || - || Branch on ZF = 0 PC + 2↓, [FFFE] → PCL, [FFFF] → PCH || Branch on Not EqualBReaK
|-
| BPL SEI || 78 (2) || || || || || || || || || || || 10 (2+t+p) || - || - || - || - || - 1 || - || - || Branch on NF = 0 1 → IF || Branch on PLusSEt Interrupt flag
|-
| BRK CLI || 00 58 (72) || || || || || || || || || || || || - || - || 1 || - || 1 0 || - || - || PC + 2↓, [FFFE] → PCL, [FFFF] 0 → PCH IF || BReaKCLear Interrupt flag
|-
| BVC SEC || 38 (2) || || || || || || || || || || || 50 (2+t+p) || - || - || - || - || - || - || - 1 || Branch on VF = 0 1 → CF || Branch on oVerflow ClearSEt Carry flag
|-
| BVS CLC || 18 (2) || || || || || || || || || || || 70 (2+t+p) || - || - || - || - || - || - || - 0 || Branch on VF = 1 0 → CF || Branch on oVerflow SetCLear Carry flag
|-
| CLC SED || 18 F8 (2) || || || || || || || || || || || || - || - || - 1 || - || - || - || 0 || 0 1 → CF DF || CLear Carry SEt Decimal flag
|-
| CLD || D8 (2) || || || || || || || || || || || || - || - || - || 0 || - || - || - || 0 → DF || CLear Decimal flag
|-
| CLI CLV || 58 B8 (2) || || || || || || || || || || || || - || - 0 || - || - || 0 || - || - || 0 → IF VF || CLear Interrupt oVerflow flag
|-
| CLV NOP || B8 EA (2) || || || || || || || || || || || || - || 0 || - || - || - || - || - || 0 → VF No operation || CLear oVerflow flagNo OPeration
|-
| JMP BPL || || || 4C (3) || || || 6C (5) || || || || || || 10 (2+t+p) || - || - || - || - || - || - || - || [PC + 1] → PCL, [PC + 2] → PCH Branch on NF = 0 || JuMPBranch on PLus
|-
| JSR BMI || || || 20 (6) || || || || || || || || || 30 (2+t+p) || - || - || - || - || - || - || - || PC + 2↓, [PC + Branch on NF = 1] → PCL, [PC + 2] → PCH || Jump to SubRoutineBranch on MInus
|-
| NOP BVC || EA (2) || || || || || || || || || || || 50 (2+t+p) || - || - || - || - || - || - || - || No operation Branch on VF = 0 || No OPerationBranch on oVerflow Clear
|-
| RTI BVS || 40 (6) || || || || || || || || || || || 70 (2+t+p) || N - || V - || - || D - || I - || Z - || C || (S)↑ → P, (S)↑ → PCL, (S)↑ → PCH Branch on VF = 1 || ReTurn from InterruptBranch on oVerflow Set
|-
| RTS BCC || 60 (6) || || || || || || || || || || || 90 (2+t+p) || - || - || - || - || - || - || - || (S)↑ → PCL, (S)↑ → PCH, PC + 1 → PC Branch on CF = 0 || ReTurn from SubroutineBranch on Carry Clear
|-
| SEC BCS || 38 (2) || || || || || || || || || || || B0 (2+t+p) || - || - || - || - || - || - || Branch on CF = 1 || 1 → CF || SEt Branch on Carry flagSet
|-
| SED BNE || F8 (2) || || || || || || || || || || || D0 (2+t+p) || - || - || - || 1 || - || - || - || 1 → DF Branch on ZF = 0 || SEt Decimal flagBranch on Not Equal
|-
| SEI BEQ || 78 (2) || || || || || || || || || || || F0 (2+t+p) || - || - || - || - || 1 || - || - || Branch on ZF = 1 → IF || SEt Interrupt flagBranch on EQual
|}
=== Illegal instructions ===
Opcodes A lot of these illegal instructions involve a bitwise AND operation, which is a side effect of the open-drain behavior of NMOS logic. When two instructions put a value on the bus at the same time, this creates a bus conflict resulting effectively in red are unstablean AND operation. The lower voltage wins because transistors can pull down stronger than resistors can pull up.
{| class="wikitable" style="white-space: nowrap;"
|-
! rowspan=2|Mnemonic !! colspan=10|Addressing Modes !! colspan=76|Flags !! rowspan=2|Operation !! rowspan=2|Description
|-
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! N !! V !! B !! D !! I !! Z !! C
|-
| ALR DCP (ASRDCM) || || 4B || CF (26) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || || 0 || - N || - || - || - || Z || C || A AND oper, 0 M -> [76543210] 1 -> C M, A - M || AND DEC oper + LSRCMP oper
|-
| ANC ISC (ISB, INS) || || || 0B EF (26) || FF (7) || FB (7) || E7 (5) || F7 (6) || || E3 (8) || || F3 (8) || N || - || - V || - || - || Z || C || M + 1 -> M, A AND oper, bit(7) - M - CF -> C A || AND INC oper + set C as ASLSBC oper
|-
| ANC2 RLA || || 2B || 2F (26) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || || 33 (8) || N || - || - || - || - || Z || C || M = CF <- [76543210] <- CF, A AND oper, bit(7) M -> C A || AND ROL oper + set C as ROLAND oper
|-
| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || Z || C || M = CF -> [76543210] -> CF, A + M + CF -> A, CF || ROR oper + ADC oper|-| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- 0, A OR M -> A || ASL oper + ORA oper|-| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || Z || C || M = 0 -> [76543210] -> CF, A EOR M -> A || LSR oper + EOR oper|-| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper|-| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X|-| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper|-| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| ANE (XAA) || || style="color: #CC0000;"|'''8B''' (2) || || || || || || || || || N || - || - || - || - || Z || - || (A OR magic) AND X AND oper -> A || * AND X + AND oper
highly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors.
Turrican 3 on C64 requires a different magic constant than $EE for ANE. $EF is recommended by Groepaz (VICE team)
|-
| ARR LXA (LAX) ||| |style="color: #CC0000;"| 6B '''AB''' (2) || || || || || || || || || N || V || - || - || - || Z || C - || (A OR magic) AND oper, C -> [76543210] A -> C X || Store * AND oper + RORin A and Xhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Wizball on C64 requires a $EE magic constant for LXA
|-
| DCP ALR (DCMASR) || || || CF 4B (62) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || N || - 0 || - || - || - || Z || C || M A AND oper, 0 - 1 > [76543210] -> M, A - M CF || DEC AND oper + CMP operLSR
|-
| ISC ARR || || 6B (ISB, INS2) || || || EF (6) || FF || || || || || N || V || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR|-| ANC || || 0B (72) || FB || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || E7 AND oper + set CF as ASL|-| ANC2 || || 2B (52) || F7 || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(67) -> CF || AND oper + set CF as ROL|-| E3 SBX (8AXS, SAX) || F3 || CB (82) || N || V || || || || || || || N || - || - || - || Z || C || M + 1 (A AND X) - oper -> MX || CMP and DEX at once, sets flags like CMP|-| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || Z || C || A - M - C ~CF -> A || INC SBC oper + SBC operNOP
|-
| JAM (KIL, HLT) || 02, 12, 22,
B2, D2, F2 (X)
|| || || || || || || || || || - || - || - || - || - || - || - || Stop execution || Halt the CPU. The processor will be trapped infinitely in T1 phase with $FF on the data bus. Reset required.|-| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper|-| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper|-| LXA (LAX) || || style="color: #CC0000;"|'''AB''' (2) || || || || || || || || || N || - || - || - || - || Z || - || (A OR magic) AND oper -> A -> X || Store * AND oper in A and Xhighly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors. Wizball on C64 requires a $EE magic constant for LXA
|-
| NOP (DOP, TOP) || 1A, 3A, 5A,
|| || 04, 44, 64 (3) || 14, 34, 54,
74, D4, F4 (4)
|| || || || - || - || - || - || - || - || - || No operation || No Operation|-| RLA || || || 2F (6) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || 33 (8) || N || - || - || - || - || Z || C || M = C <- [76543210] <- C, A AND M -> A || ROL oper + AND oper|-| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || - || Z || C || M = C -> [76543210] -> C, A + M + C -> A, C || ROR oper + ADC oper|-| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X|-| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP|-| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || - || Z || C || M = C <- [76543210] <- 0, A OR M -> A || ASL oper + ORA oper|-| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || - || Z || C || M = 0 -> [76543210] -> C, A EOR M -> A || LSR oper + EOR oper|-| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || - || Z || C || A - M - ~C -> A || SBC oper + NOP
|}
A lot of these illegal instructions involve a bitwise AND operation, which is a side effect of the open-drain behavior of NMOS logic. When two instructions put a value on the bus at the same time, this creates a bus conflict resulting effectively Opcodes in an AND operation. The lower voltage wins because transistors can pull down stronger than resistors can pull upred are unstable.
<br>
| 68 || PLA
|-
| 6C xx xx || JMP ''zpgind''
|-
| 70 xx || BVS ''rel''
Any instruction xxxxxx11 will execute the instructions at xxxxxx01 and xxxxxx10 at once, using the address mode of the instruction at xxxxxx01.
For example: , "SAX abs” ($8F) is the composite of “STA abs” ($8D) and “STX abs” ($8E).
<br>
* On NMOS, an indirect JMP will behave unexpectedly when the indirect address crosses a page boundary, because the 6502 does not add the carry to calculate the address of the high byte. For example, JMP ($19FF) will use the contents of $19FF and $1900 for the JMP address. On CMOS, this issue was fixed, at the cost of 1 additional cycle. In our example, JMP ($19FF) will use the contents of $19FF and $2000 for the JMP address.
* Some instructions, particularly those involving branches or indexed addressing modes, incur an extra cycle if the processor has to cross a memory page boundary. This is problematic for time-sensitive code.
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
* The Z80 pre-decrements on PUSH and post-increments on POP, while the 6502 post-decrements on PHA and pre-increments on PLA, making them behave in opposite ways.
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The TXS instruction does not affect any flag, while all other transfer instructions do.
* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.
* The CLV (Clear Overflow Flag) instruction exist, but not the SEV (Set Overflow Flag) instruction.
* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.
* The alternate NOPs are not created equal. Some have one- or two-byte operands (which they don't do anything with), and they take different amounts of time to execute.
* The CLV (Clear Overflow Flag) instruction exist but not the SEV (Set Overflow Flag) instruction.<br>
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.== Compared behaviour ==
* The alternate NOPs are not created equal6502’s Decimal (BCD) mode automatically adjusts ADC and SBC results, while the Z80 requires a DAA instruction after each BCD addition and subtraction. Some have * The 6502 uses only one- or addressing mode per instruction, while the Z80 can combine twodifferent addressing modes within a single instruction.* The 6502 post-byte operands (which they dondecrements on PHA and pre-increments on PLA, while the Z80 pre-decrements on PUSH and post-increments on POP.* The 6502 saves flags automatically during interrupts; while the Z80 requires PUSH AF and POP AF.* The 6502 only updates flags that are directly relevant to the operation's result. For example, EOR doesn't do anything with)conceptually involve a carry, and they take different amounts of time so the Carry flag is left untouched. On the Z80, XOR always clears the Carry flag to executeensure a clean flag state.
<br>
For a specific example, the 6502 PLA decodes instructions matching 100XX1XX to the control line STY (ignoring the timing bits for simplicity). This takes 1 row in the PLA, but it would take 16 entries in a ROM. [https://news.ycombinator.com/item?id=13128074 Source]
See: [https://web.archive.org/web/20210519010632/http://visual6502.org/wiki/index.php?title=6507_Decode_ROM 6507 Decode ROM (PLA)] [https://pastraiser.com/cpu/65CE02/65CE02_rom.html 65CE02 Decode ROM (PLA)] [https://www.righto.com/2016/02/reverse-engineering-arm1-instruction.html ARM1, Z80, 6502 instruction sequencing compared] [https://www.pagetable.com/?p=410 Internals of BRK/IRQ/NMI/RESET on a MOS 6502] [https://www.pagetable.com/?p=39 How MOS 6502 illegal opcodes really work] [https://c74project.com/wp-content/uploads/2020/04/c74-6502-microcode.pdf 6502 microcode] [https://c74project.com/wp-content/uploads/2020/04/c74-6502-microinstructions.pdf 6502 microinstructions]
<br>
* The ROR instruction didn't exist in the very earliest (pre-1977) chips. See: [https://www.pagetable.com/?p=406 Measuring the ROR Bug in the Early MOS 6502]
* The 6502 core used inside the [[NES]] is missing the Decimal Mode feature. [https://archive.org/details/nes-programmers-reference-guide-by-electronic-arts-1989/ NES programmer's reference guide] [https://www.nesdev.org/NESDoc.pdf NESDoc] [https://www.nesdev.org/wiki/Mapper NES mappers] [https://problemkaputt.de/everynes.htm Noca$h's Everynes] [https://www.nesdev.org/wiki/Emulator_tests NES emulator tests] [https://tcrf.net/Category:Nintendo_Console_Testing_Software Official Nintendo testing software]
* The 6507 CPU, used in the [[Atari VCS]], has only 13 address lines. So it can only address 8KB instead of 64KB. It also lacks the IRQ and NMI interrupt lines. [https://youtu.be/qvpwf50a48E Atari VCS: The Ultimate Talk] [https://cdn.hackaday.io/files/1646277043401568/stella.pdf Stella programmer's guide] [https://www.atarimania.com/documents/stella_system_training_manual.pdf Stella system training manual] [https://problemkaputt.de/2k6specs.htm Noca$h's 2k6specs]
* The 6502C used in [[Atari 8-bit]] computer range, adds an additional HALT pin for DMA. The 6502C is otherwise a regular NMOS 6502, not to be confused with the CMOS 65C02.
* The CMOS 65C02 fixed multiple bugs of the original NMOS 6502, but also removed access to all illegal instructions. Some cycle counts have been modified and some extra instructions have been added. In fact, there are multiple implementations of the 65C02 (WDC 65C02, WDC 65C02S, Rockwell R65C02, CSG 65CE02, ...), each with its own variant of the instruction set[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference].
* The HuC6280, used in the [[PC-Engine]] gaming console, is an improved version of the CMOS 65C02. [[Media:HuC6280 - CMOS 8-bit Microprocessor Hardware Manual.pdf|HuC6280 hardware manual]] [[Media:HuC6260 - CMOS Video Color Encoder Manual.pdf|HuC6260 VCE manual]] [[Media:HuC6270 - CMOS Video Display Controller Manual.pdf|HuC6270 VDC manual]]
* The WDC 65C816, used in the [[SNES]] and the [[Apple IIGS]], is a 16-bit version of the 65C02 [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet] [https://archive.org/details/SNESDevManual/ SNES development manual] [https://problemkaputt.de/fullsnes.htm Noca$h's fullsnes] [https://fabiensanglardsnes.netnesdev.org/ Fabien Sanglard's 2024 articleswiki/SNESdev_Wiki SNESdev wiki]. The 65C816 contains a compatibillity mode, enabled by default upon reset, that makes it behave like a regular 65C02. The full 65C816 cycle-by-cycle steps are in the [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet].
* The Sony SPC700 sound CPU used inside the SNES also behaves similarly to a 6502 with some extensions. [https://wiki.superfamicom.org/spc700-reference Source] [https://www.youtube.com/watch?v=zrn0QavLMyo&list=PLHQ0utQyFw5JD2wWda50J8XuzQ2cFr8RX SPC700 Series] [https://github.com/gilyon/snes-tests SNES-tests]
<br>
*[https://www.masswerk.at/6502/6502_instruction_set.html 6502 Instruction Set] [https://www.masswerk.at/nowgobang/2021/6502-illegal-opcodes 6502 illegal opcodes demystified]
*[[Media:NoMoreSecrets-NMOS6510UnintendedOpcodes-20212412.pdf|No more secrets - NMOS 6510 Unintended Opcodes]]
*[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference]
*[https://llx.com/Neil/a2/opcodes.html The 6502/65C02/65C816 Instruction Set Decoded]
*[https://pastraiser.com/cpu/6502/6502_opcodes.html 6502 opcodes] [https://pastraiser.com/cpu/65CE02/65CE02_opcodes.html 65CE02 opcodes]
*[https://www.nesdev.org/wiki/CPU_unofficial_opcodes Opcode matrix arrangement]
*[https://www.oxyron.de/html/opcodes.html Oxyron Opcode Matrices]
*[http://retro.hansotten.nl/uploads/books/Programming_the_6502.pdf Rodnay Zaks Programming the 6502]
*[http://www.6502.org/documents/datasheets/synertek/synertek_programming_manual.pdf Synertek SY650x programming manual (250 pages)]
*[http://www.6502.org/documents/datasheets/synertek/synertek_hardware_manual.pdf Synertek SY650x hardware manual (178 pages)]
*[[Media:SY6500 - SY65C02 datasheet.pdf]] - features a detailed breakdown of 65C02 instructions
*[https://xotmatrix.github.io/6502/ xotmatrix] 6502 instruction set and detailed cycle-by-cycle breakdown
*[[Media:6502 (65xx) Microprocessor Instant Reference Card.pdf]]
*[https://www.nesdev.org/wiki/CPU_interrupts 6502 Interrupts]