*ABL/ABH: Address Bus Low/High, latches for the address bus.
*AI/BI: Input Registers for the ALU.
*IR: Instruction Register, holds the fetched instruction opcode byte while the CPU decodes and executes it.
<br>
The Zero Page on the 6502 is a special area of memory from addresses $0000 to $00FF that act like pseudo registers. The 6502 provides optimized instructions that operate more efficiently when using addresses within the Zero Page.
Fun fact: the TMS9900 CPU took this further, and had by having no onboard registers (other than , except PC & status register). Everything was in RAM.
<br>
! ''No arg'' !! A !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! D !! I !! Z !! C
|-
| ADC BIT || || || 69 (2) || 6D 2C (4) || 7D (4+p) || 79 (4+p) || || 65 24 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || Z || C - || A + ∧ M + CF , M<sub>7</sub> → ANF, CF M<sub>6</sub> → VF || ADd with Carrytest BITs
|-
| AND || || || 29 (2) || 2D (4) || 3D (4+p) || 39 (4+p) || || 25 (3) || 35 (4) || || 21 (6) || 31 (5+p) || || N || - || - || - || Z || - || A ∧ M → A || bitwise AND with accumulator
|-
| ASL EOR || || 0A || 49 (2) || 4D (4) || 0E 5D (64+p) || 1E 59 (74+p) || || 45 (3) || 06 55 (54) || 16 || 41 (6) || 51 (5+p) || || N || - || - || - || Z || - || A ⊻ M → A || bitwise Exclusive OR|-| ORA || || || 09 (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || N || - || - || - || Z || - || A ∨ M → A || bitwise OR with Accumulator|-| ADC || || || 69 (2) || 6D (4) || 7D (4+p) || 79 (4+p) || || 65 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || Z || C || A + M + CF ← /→ A, CF || ADd with Carry|-| SBC || || || E9 (2) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (6) || F1 (5+p) || || N || V || - || - || Z || C || A - M<sub>7</sub>...M<sub>0</sub>/ ← 0 - (1 - CF) → A || Arithmetic Shift LeftSuBtract with Carry
|-
| CMP || || || C9 (2) || CD (4) || DD (4+p) || D9 (4+p) || || C5 (3) || D5 (4) || || C1 (6) || D1 (5+p) || || N || - || - || - || Z || C || A - M || CoMPare accumulator
|-
| CPY || || || C0 (2) || CC (4) || || || || C4 (3) || || || || || || N || - || - || - || Z || C || Y - M || ComPare Y register
|-
| ASL || || 0A (2) || || 0E (6) || 1E (7) || || || 06 (5) || 16 (6) || || || || || N || - || - || - || Z || C || CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← 0 || Arithmetic Shift Left
|-
| LSR || || 4A (2) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || 0 || - || - || - || Z || C || 0 → /M<sub>7</sub>...M<sub>0</sub>/ → CF || Logical Shift Right
|-
| ROL || || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || 36 (6) || || || || || N || - || - || - || Z || C || CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← CF || ROtate Left
|-
| ROR || || 6A (2) || || 6E (6) || 7E (7) || || || 66 (5) || 76 (6) || || || || || N || - || - || - || Z || C || CF → /M<sub>7</sub>...M<sub>0</sub>/ → CF || ROtate Right
|-
| DEC || || || || CE (6) || DE (7) || || || C6 (5) || D6 (6) || || || || || N || - || - || - || Z || - || M - 1 → M || DECrement memory
|-
| INC || || || || EE (6) || FE (7) || || || E6 (5) || F6 (6) || || || || || N || - || - || - || Z || - || M + 1 → M || INCrement memory
|-
| DEX || CA (2) || || || || || || || || || || || || || N || - || - || - || Z || - || X - 1 → X || DEcrement X
|-
| DEY || 88 (2) || || || || || || || || || || || || || N || - || - || - || Z || - || Y - 1 → Y || DEcrement Y
|-
| EOR || || || 49 (2) || 4D (4) || 5D (4+p) || 59 (4+p) || || 45 (3) || 55 (4) || || 41 (6) || 51 (5+p) || || N || - || - || - || Z || - || A ⊻ M → A || bitwise Exclusive OR
|-
| INC || || || || EE (6) || FE (7) || || || E6 (5) || F6 (6) || || || || || N || - || - || - || Z || - || M + 1 → M || INCrement memory
|-
| INX || E8 (2) || || || || || || || || || || || || || N || - || - || - || Z || - || X + 1 → X || INcrement X
|-
| INY || C8 (2) || || || || || || || || || || || || || N || - || - || - || Z || - || Y + 1 → Y || INcrement Y
|-
| LSR || || 4A (2) || || 4E (6) || 5E (7) || || || 46 (5) || 56 (6) || || || || || 0 || - || - || - || Z || C || 0 → /M<sub>7</sub>...M<sub>0</sub>/ → CF || Logical Shift Right
|-
| ORA || || || 09 (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || N || - || - || - || Z || - || A ∨ M → A || bitwise OR with Accumulator
|-
| ROL || || 2A (2) || || 2E (6) || 3E (7) || || || 26 (5) || 36 (6) || || || || || N || - || - || - || Z || C || CF ← /M<sub>7</sub>...M<sub>0</sub>/ ← CF || ROtate Left
|-
| ROR || || 6A (2) || || 6E (6) || 7E (7) || || || 66 (5) || 76 (6) || || || || || N || - || - || - || Z || C || CF → /M<sub>7</sub>...M<sub>0</sub>/ → CF || ROtate Right
|-
| SBC || || || E9 (2) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (6) || F1 (5+p) || || N || V || - || - || Z || C || A - M - (1 - CF) → A || SuBtract with Carry
|}
|-
| LDY || || A0 (2) || AC (4) || BC (4+p) || || || A4 (3) || B4 (4) || || || || || N || - || - || - || Z || - || M → Y || LoaD Y register
|-
| PHA || 48 (3) || || || || || || || || || || || || - || - || - || - || - || - || A↓ || PusH Accumulator
|-
| PHP || 08 (3) || || || || || || || || || || || || - || - || - || - || - || - || P↓ || PusH Processor status
|-
| PLA || 68 (4) || || || || || || || || || || || || N || - || - || - || Z || - || (S)↑ → A || PuLl Accumulator
|-
| PLP || 28 (4) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P || PuLl Processor status
|-
| STA || || || 8D (4) || 9D (5) || 99 (5) || || 85 (3) || 95 (4) || || 81 (6) || 91 (6) || || - || - || - || - || - || - || A → M || STore Accumulator
|-
| TAX || AA (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → X || Transfer A to X
|-
| TXA || 8A (2) || || || || || || || || || || || || N || - || - || - || Z || - || X → A || Transfer X to A
|-
| TAY || A8 (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → Y || Transfer A to Y
|-
| TYA || 98 (2) || || || || || || || || || || || || N || - || - || - || Z || - || Y → A || Transfer Y to A
|-
| TSX || BA (2) || || || || || || || || || || || || N || - || - || - || Z || - || S → X || Transfer Stack pointer to X
|-
| TXA || 8A (2) || || || || || || || || || || || || N || - || - || - || Z || - || X → A || Transfer X to A
|-
| TXS || 9A (2) || || || || || || || || || || || || - || - || - || - || - || - || X → S || Transfer X to Stack pointer
|-
| TYA PLP || 98 28 (24) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P || PuLl Processor status|-| PLA || 68 (4) || || || || || || || || || || || || N || - || - || - || Z || - || Y (S)↑ → A || Transfer Y to APuLl Accumulator|-| PHP || 08 (3) || || || || || || || || || || || || - || - || - || - || - || - || P↓ || PusH Processor status|-| PHA || 48 (3) || || || || || || || || || || || || - || - || - || - || - || - || A↓ || PusH Accumulator
|}
|-
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! D !! I !! Z !! C
|-
| BCC JMP || || || 4C (3) || || || 6C (5) || || || || || || 90 (2+t+p) || - || - || - || - || - || - || Branch on CF = 0 [PC + 1] → PCL, [PC + 2] → PCH || Branch on Carry ClearJuMP
|-
| BCS JSR || || || 20 (6) || || || || || || || || || B0 (2+t+p) || - || - || - || - || - || - || Branch on CF = PC + 2↓, [PC + 1 ] → PCL, [PC + 2] → PCH || Branch on Carry SetJump to SubRoutine
|-
| BEQ RTS || 60 (6) || || || || || || || || || || || F0 (2+t+p) || - || - || - || - || - || - || Branch on ZF = (S)↑ → PCL, (S)↑ → PCH, PC + 1 → PC || Branch on EQualReTurn from Subroutine
|-
| BIT RTI || 40 (6) || || 2C (4) || || || || 24 (3) || || || || || || N || V || - D || - I || Z || - C || A ∧ M(S)↑ → P, M<sub>7</sub> (S)↑ → NFPCL, M<sub>6</sub> (S)↑ → VF PCH || test BITsReTurn from Interrupt
|-
| BMI BRK || 00 (7) || || || || || || || || || || || 30 (2+t+p) || - || - || - || - 1 || - || - || Branch on NF = 1 PC + 2↓, [FFFE] → PCL, [FFFF] → PCH || Branch on MInusBReaK
|-
| BNE SEI || 78 (2) || || || || || || || || || || || D0 (2+t+p) || - || - || - || - 1 || - || - || Branch on ZF = 0 1 → IF || Branch on Not EqualSEt Interrupt flag
|-
| BPL CLI || 58 (2) || || || || || || || || || || || 10 (2+t+p) || - || - || - || - 0 || - || - || Branch on NF = 0 → IF || Branch on PLusCLear Interrupt flag
|-
| BRK SEC || 00 38 (72) || || || || || || || || || || || || - || - || - || 1 - || - || - 1 || PC + 2↓, [FFFE] → PCL, [FFFF] 1 → PCH CF || BReaKSEt Carry flag
|-
| BVC CLC || 18 (2) || || || || || || || || || || || 50 (2+t+p) || - || - || - || - || - || - 0 || Branch on VF = 0 → CF || Branch on oVerflow ClearCLear Carry flag
|-
| BVS SED || || || || || || || || || || || || 70 F8 (2+t+p) || - || - || - || - || - || - || Branch on VF = 1 || Branch on oVerflow Set|-| CLC || 18 (2) || || || || || || || || || || || - || - || - 1 || - || - || - || 0 || 0 1 → CF DF || CLear Carry SEt Decimal flag
|-
| CLD || D8 (2) || || || || || || || || || || || || - || - || 0 || - || - || - || 0 → DF || CLear Decimal flag
|-
| CLI || 58 (2) || || || || || || || || || || || || - || - || - || 0 || - || - || 0 → IF || CLear Interrupt flag
|-
| CLV || B8 (2) || || || || || || || || || || || || - || 0 || - || - || - || - || 0 → VF || CLear oVerflow flag
|-
| JMP NOP || EA (2) || || 4C (3) || || || 6C (5) || || || || || || || - || - || - || - || - || - || [PC + 1] → PCL, [PC + 2] → PCH No operation || JuMPNo OPeration
|-
| JSR BPL || || || 20 (6) || || || || || || || || || 10 (2+t+p) || - || - || - || - || - || - || PC + 2↓, [PC + 1] → PCL, [PC + 2] → PCH Branch on NF = 0 || Jump to SubRoutineBranch on PLus
|-
| NOP BMI || EA (2) || || || || || || || || || || || 30 (2+t+p) || - || - || - || - || - || - || No operation Branch on NF = 1 || No OPerationBranch on MInus
|-
| RTI BVC || 40 (6) || || || || || || || || || || || 50 (2+t+p) || N - || V - || D - || I - || Z - || C - || (S)↑ → P, (S)↑ → PCL, (S)↑ → PCH Branch on VF = 0 || ReTurn from InterruptBranch on oVerflow Clear
|-
| RTS BVS || 60 (6) || || || || || || || || || || || 70 (2+t+p) || - || - || - || - || - || - || (S)↑ → PCL, (S)↑ → PCH, PC + Branch on VF = 1 → PC || ReTurn from SubroutineBranch on oVerflow Set
|-
| SEC BCC || 38 (2) || || || || || || || || || || || 90 (2+t+p) || - || - || - || - || - || 1 - || 1 → Branch on CF = 0 || SEt Branch on Carry flagClear
|-
| SED BCS || F8 (2) || || || || || || || || || || || B0 (2+t+p) || - || - || 1 - || - || - || - || Branch on CF = 1 → DF || SEt Decimal flagBranch on Carry Set
|-
| SEI BNE || 78 || || || || || || || || || || || D0 (2+t+p) || - || - || - || - || - || - || Branch on ZF = 0 || Branch on Not Equal|-| BEQ || || || || || || || || || || || || F0 (2+t+p) || - || - || - || 1 - || - || - || Branch on ZF = 1 → IF || SEt Interrupt flagBranch on EQual
|}
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! N !! V !! D !! I !! Z !! C
|-
| ALR DCP (ASRDCM) || || 4B || CF (26) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || || 0 N || - || - || - || Z || C || A AND oper, 0 M -> [76543210] 1 -> CF M, A - M || AND DEC oper + LSRCMP oper
|-
| ANC ISC (ISB, INS) || || || 0B EF (26) || FF (7) || FB (7) || E7 (5) || F7 (6) || || E3 (8) || || F3 (8) || N || - V || - || - || Z || C || A AND oper, bit(7) M + 1 -> M, A - M - CF -> A || AND INC oper + set CF as ASLSBC oper
|-
| ANC2 RLA || || 2B || 2F (26) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || || 33 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- CF, A AND M -> A || ROL oper+ AND oper|-| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || Z || C || M = CF -> [76543210] -> CF, bitA + M + CF -> A, CF || ROR oper + ADC oper|-| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- 0, A OR M -> A || ASL oper + ORA oper|-| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || Z || C || M = 0 -> [76543210] -> CF , A EOR M -> A || LSR oper + EOR oper|-| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper|-| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X|-| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper |-| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+ set CF as ROL1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| ANE (XAA) || || style="color: #CC0000;"|'''8B''' (2) || || || || || || || || || N || - || - || - || Z || - || (A OR magic) AND X AND oper -> A || * AND X + AND oper
Turrican 3 on C64 requires a different magic constant than $EE for ANE. $EF is recommended by Groepaz (VICE team)
|-
| LXA (LAX) || || style="color: #CC0000;"|'''AB''' (2) || || || || || || || || || N || - || - || - || Z || - || (A OR magic) AND oper -> A -> X || Store * AND oper in A and X
highly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors.
Wizball on C64 requires a $EE magic constant for LXA
|-
| ALR (ASR) || || 4B (2) || || || || || || || || || 0 || - || - || - || Z || C || A AND oper, 0 -> [76543210] -> CF || AND oper + LSR
|-
| ARR || || 6B (2) || || || || || || || || || N || V || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR
|-
| DCP (DCM) ANC || || || CF 0B (62) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || || N || - || - || - || Z || C || M - 1 A AND oper, bit(7) -> M, A - M CF || DEC AND oper + CMP operset CF as ASL
|-
| ISC ANC2 || || 2B (ISB, INS2) || || || EF (6) || FF || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || FB AND oper + set CF as ROL|-| SBX (7AXS, SAX) || E7 || CB (52) || F7 || || || || || || || || N || - || - || - || Z || C || (6A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP|-| E3 USBC (8SBC) || F3 || EB (82) || || || || || || || || || N || V || - || - || Z || C || M + 1 -> M, A - M - ~CF -> A || INC SBC oper + SBC operNOP
|-
| JAM (KIL, HLT) || 02, 12, 22,
B2, D2, F2 (X)
|| || || || || || || || || || - || - || - || - || - || - || Stop execution || Halt the CPU. The processor will be trapped infinitely in T1 phase with $FF on the data bus. Reset required.
|-
| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper
|-
| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper
|-
| LXA (LAX) || || style="color: #CC0000;"|'''AB''' (2) || || || || || || || || || N || - || - || - || Z || - || (A OR magic) AND oper -> A -> X || Store * AND oper in A and X
highly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors.
Wizball on C64 requires a $EE magic constant for LXA
|-
| NOP (DOP, TOP) || 1A, 3A, 5A,
74, D4, F4 (4)
|| || || || - || - || - || - || - || - || No operation || No Operation
|-
| RLA || || || 2F (6) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || 33 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- CF, A AND M -> A || ROL oper + AND oper
|-
| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || Z || C || M = CF -> [76543210] -> CF, A + M + CF -> A, CF || ROR oper + ADC oper
|-
| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X
|-
| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP
|-
| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addr
unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addr
unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addr
unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- 0, A OR M -> A || ASL oper + ORA oper
|-
| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || Z || C || M = 0 -> [76543210] -> CF, A EOR M -> A || LSR oper + EOR oper
|-
| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addr
unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
|-
| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || Z || C || A - M - ~CF -> A || SBC oper + NOP
|}
| 68 || PLA
|-
| 6C xx xx || JMP ''zpgind''
|-
| 70 xx || BVS ''rel''
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The TXS instruction does not affect any flag, while all other transfer instructions do.* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.* The CLV (Clear Overflow Flag) instruction exist , but not the SEV (Set Overflow Flag) instruction.* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.
* The alternate NOPs are not created equal. Some have one- or two-byte operands (which they don't do anything with), and they take different amounts of time to execute.
* The 6502C used in [[Atari 8-bit]] computer range, adds an additional HALT pin for DMA. The 6502C is otherwise a regular NMOS 6502, not to be confused with the CMOS 65C02.
* The CMOS 65C02 fixed multiple bugs of the original NMOS 6502, but also removed access to all illegal instructions. Some cycle counts have been modified and some extra instructions have been added. In fact, there are multiple implementations of the 65C02 (WDC 65C02, WDC 65C02S, Rockwell R65C02, CSG 65CE02, ...), each with its own variant of the instruction set[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference].
* The HuC6280, used in the [[PC-Engine]] gaming console, is an improved version of the CMOS 65C02. [[Media:HuC6280 - CMOS 8-bit Microprocessor Hardware Manual.pdf|HuC6280 hardware manual]] [[Media:HuC6260 - CMOS Video Color Encoder Manual.pdf|HuC6260 VCE manual]] [[Media:HuC6270 - CMOS Video Display Controller Manual.pdf|HuC6270 VDC manual]]
* The WDC 65C816, used in the [[SNES]] and the [[Apple IIGS]], is a 16-bit version of the 65C02 [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet] [https://archive.org/details/SNESDevManual/ SNES development manual] [https://problemkaputt.de/fullsnes.htm Noca$h's fullsnes] [https://snes.nesdev.org/wiki/SNESdev_Wiki SNESdev wiki]. The 65C816 contains a compatibillity mode, enabled by default upon reset, that makes it behave like a regular 65C02. The full 65C816 cycle-by-cycle steps are in the [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 datasheet].
* The Sony SPC700 sound CPU used inside the SNES also behaves similarly to a 6502 with some extensions. [https://wiki.superfamicom.org/spc700-reference Source] [https://www.youtube.com/watch?v=zrn0QavLMyo&list=PLHQ0utQyFw5JD2wWda50J8XuzQ2cFr8RX SPC700 Series] [https://github.com/gilyon/snes-tests SNES-tests]
*[https://www.masswerk.at/6502/6502_instruction_set.html 6502 Instruction Set] [https://www.masswerk.at/nowgobang/2021/6502-illegal-opcodes 6502 illegal opcodes demystified]
*[[Media:NoMoreSecrets-NMOS6510UnintendedOpcodes-20212412.pdf|No more secrets - NMOS 6510 Unintended Opcodes]]
*[https://www.pagetable.com/c64ref/6502/?tab=2 6502 Family CPU Reference]
*[https://llx.com/Neil/a2/opcodes.html The 6502/65C02/65C816 Instruction Set Decoded]
*[https://pastraiser.com/cpu/6502/6502_opcodes.html 6502 opcodes] [https://pastraiser.com/cpu/65CE02/65CE02_opcodes.html 65CE02 opcodes]