| STY || || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || - || - || - || - || - || - || Y → M || STore Y register
|-
| PHP TAX || 08 AA (32) || || || || || || || || || || || || - N || - || - || - || - Z || - || P↓ A → X || PusH Processor statusTransfer A to X
|-
| PHA TXA || 48 8A (3) || || || || || || || || || || || || - || - || - || - || - || - || A↓ || PusH Accumulator|-| PLP || 28 (4) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P || PuLl Processor status|-| PLA || 68 (42) || || || || || || || || || || || || N || - || - || - || Z || - || (S)↑ X → A || PuLl Accumulator|-| TAX || AA (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → Transfer X || Transfer to A to X
|-
| TAY || A8 (2) || || || || || || || || || || || || N || - || - || - || Z || - || A → Y || Transfer A to Y
|-
| TXA || 8A (2) || || || || || || || || || || || || N || - || - || - || Z || - || X → A || Transfer X to A
|-
| TYA || 98 (2) || || || || || || || || || || || || N || - || - || - || Z || - || Y → A || Transfer Y to A
|-
| TXS || 9A (2) || || || || || || || || || || || || - || - || - || - || - || - || X → S || Transfer X to Stack pointer
|-
| PLP || 28 (4) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P || PuLl Processor status
|-
| PLA || 68 (4) || || || || || || || || || || || || N || - || - || - || Z || - || (S)↑ → A || PuLl Accumulator
|-
| PHP || 08 (3) || || || || || || || || || || || || - || - || - || - || - || - || P↓ || PusH Processor status
|-
| PHA || 48 (3) || || || || || || || || || || || || - || - || - || - || - || - || A↓ || PusH Accumulator
|}
|-
| ARR || || 6B (2) || || || || || || || || || N || V || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR
|-
| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP
|-
| ANC || || 0B (2) || || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || AND oper + set CF as ASL
|-
| ANC2 || || 2B (2) || || || || || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || AND oper + set CF as ROL
|-
| SBX (AXS, SAX) || || CB (2) || || || || || || || || || N || - || - || - || Z || C || (A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP
|-
| USBC (SBC) || || EB (2) || || || || || || || || || N || V || - || - || Z || C || A - M - ~CF -> A || SBC oper + NOP
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The TXS instruction does not affect any flag, while all other transfer instructions do.* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.* The CLV (Clear Overflow Flag) instruction exist , but not the SEV (Set Overflow Flag) instruction.
* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.