Changes

* Personal Computers and Workstations: Early [[Macintosh]] models, the [[Amiga]], the [[Atari ST]], and various Unix workstations leveraged the 68000 for its powerful instruction set and efficient memory addressing. [https://mirrors.apple2.org.za/ftp.apple.asimov.net/documentation/macintosh/Mac%20Hardware%20Info%20-%20Mac%20128K.pdf Macintosh hardware description]*The [[Sinclair QL]] used the nearly identical 68008 (which featured an 8‑bit external data bus and a 20-bit address bus for cost savings).* Video Game Consoles: Systems such as the Sega Genesis (Mega Drive) and arcade platforms utilized the 68000 to deliver high performance in graphics and sound processing.[https://segaretro.org/images/1/18/GenesisTechnicalOverview.pdf Genesis technical overview] [https://plutiedev.com/mirror/kabuto-hardware-notes Genesis hardware notes]

See: [https://gendev.spritesmind.net/forum/viewtopic.php?t=3023 Tech topic about a microcode-level 68000 core] [https://www.atari-forum.com/viewtopic.php?t=42568 New 68k core in mame][https://og.kervella.org/m68k/ Motorola 68000 microcode] <br>

The 68000’s register file is one of its most celebrated features. It provides:* Data Registers (D0–D7): These are 32 bits wide and are used for general-purpose arithmetic and logical operations. However, when operating on byte or word data, only the lower 8 or 16 bits are affected.* Address Registers (A0–A7): Also 32 bits wide, these registers are used for pointer operations and addressing modes. A7 doubles as the stack pointer (SP), and separate supervisor (SSP) and user (USP) stacks are supported in privileged modes.* Status == Register (SR): This 16‑bit register comprises an 8‑bit system byte (accessible only in supervisor mode) and an 8‑bit user byte known as the condition code register (CCR).**The CCR contains the standard flags—zero (Z), carry (C), overflow (V), negative (N), and extend (X).**The 3 least significant bits (bits 8, 9 and 10) of the Status register’s System byte form the interrupt mask. The interrupt priorities are numbered from 1 to 7, with level 7 having the highest priority. The level 7 interrupt is nonmaskable and thus cannot be disabled.**Bit 13 of the status register is the S flag, which specifies whether the MC68000 is in supervisor mode or user mode.**Bit 15 of the status register is the T flag, which specifies whether the MC68000 is in trace mode. After each instruction is executed in the trace mode, a trap is forced so that a debugging program can monitor the results of that instruction’s execution.File ==

{| class="wikitable" style= Privilege Modes =="white-space: nowrap;"! Register !! Size !! Description !! Notes|-| D0 - D7 || 32-bit || Data Registers || General-purpose registers for data manipulation (arithmetic, logic). Can be accessed as 8-bit (byte, `.B`), 16-bit (word, `.W`), or 32-bit (long word, `.L`). Not typically used directly for memory addressing.|-| A0 - A6 || 32-bit || Address Registers || General-purpose registers primarily used as pointers or index registers for memory addressing. Can be used for some 16-bit/32-bit arithmetic (operations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.|-| A7 (SP/USP/SSP) || 32-bit || Stack Pointer || Two physically separate registers exist: User Stack Pointer (USP) and Supervisor Stack Pointer (SSP). The Motorola processor uses the active one based on the S-bit (Supervisor state) in the Status Register.Used implicitly by stack operations (`PEA`, `LINK`, `UNLK`, `MOVE to/from -(An)/(An)+`), subroutine calls (`JSR`, `BSR`), returns (`RTS`, `RTR`), and exceptions.|-| PC (Program Counter) || 32-bit || Points to the address of the next instruction to be fetched. || Although 32-bit internally, the original 68000 has two modeshad a 24-bit address bus (16MB addressable space). Later variants (68010+) used more address lines. Modified by branches, jumps, calls, returns, exceptions.|-| SR (Status Register) || 16-bit || Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7): ''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10,9,8 - I2, I1, I0 (Interrupt Mask) <br/> * bit 13 - S (Supervisor and State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) || Userprograms can typically only read/write the CCR (lower byte).System Byte modification requires Supervisor privileges.X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and active A7). T bit enables single-step tracing. I bits control interrupt priority level.|}

In User mode, certain powerful commands like STOP, RESET, and status register changes are blocked. Debugging commands (MOVE to/from USP) are also limited to Supervisor mode. The processor uses two stack pointers: Supervisor Stack Pointer (SSP) for system tasks and User Stack Pointer (USP) for normal programs. Switching from User mode to Supervisor mode happens only through exceptions or interrupts, ensuring user programs cannot gain higher privileges on their own. All exceptions, including system calls and errors, automatically trigger Supervisor mode, and all related memory accesses are treated as Supervisor references. If true hardware-enforced privilege levels are needed, later members of the 68k family (such as the 68030, 68040, or 68060) are better suited since they include a built-in Memory Management Unit (MMU) with proper privilege separation, preventing User mode programs from modifying system memory. It also aids in virtual memory management and multitasking. This separation helps protect the system from user program errors and malicious activities. But even on 68000, the privilege modes prevent user programs from interfering with the interrupt system.<br>

== Instruction Set ==

! rowspan=2|Mnemonic !! colspan="3" | Size !! rowspan=2|Description !! rowspan=2|Operation !! colspan="5" | Condition Codes

! B !! W !! L !! X !! N !! Z !! V !! C

| ABCD || B || || || Add Decimal with Extend || (Destination)⏨ + (Source)⏨ + X → Destination || * || U || * || U || *

| ADD || B || W || L || Add Binary || (Destination) + (Source) → Destination || * || * || * || * || *

| ADDA || || W || L || Add Address || (Destination) + (Source) → Destination || – || – || – || – || –

| ADDI || B || W || L || Add Immediate || (Destination) + Immediate Data → Destination || * || * || * || * || *

| ADDQ || B || W || L || Add Quick || (Destination) + Immediate Data → Destination || * || * || * || * || *

| ADDX || B || W || L || Add Extended || (Destination) + (Source) + X → Destination || * || * || * || * || *

| AND || B || W || L || AND Logical || (Destination) ∧ (Source) → Destination || – || * || * || 0 || 0

| ANDI || B || W || L || AND Immediate || (Destination) ∧ Immediate Data → Destination || – || * || * || 0 || 0

| ANDI to CCR || B || || || AND Immediate to Condition Codes || (Source) ∧ CCR → CCR || * || * || * || * || *

| ANDI to SR || || W || || AND Immediate to Status Register || (Source) ∧ SR → SR || * || * || * || * || *

| ASL, ASR || B || W || L || Arithmetic Shift || (Destination) Shifted by < count > → Destination || * || * || * || * || *

| Bcc || || || || Branch Conditionally || If cc then PC + d → PC || – || – || – || – || –

| BCHG || B || || L || Test a Bit and Change || ~(< bit number >) OF Destination → Z

| BCLR || B || || L || Test a Bit and Clear || ~(< bit number >) OF Destination → Z

| BRA || || || || Branch Always || PC + d → PC || – || – || – || – || –

| BSET || B || || L || Test a Bit and Set || ~(< bit number >) OF Destination → Z

| BSR || || || || Branch to Subroutine || PC → (SP); PC + d → PC || – || – || – || – || –

| BTST || B || || L || Test a Bit || ~(< bit number >) OF Destination → Z || – || – || * || – || –

| CHK || || W || || Check Register Against Bounds || If Dn < 0 or Dn > (ea) then TRAP || – || * || U || U || U

| CLR || B || W || L || Clear Operand || 0 → Destination || – || 0 || 1 || 0 || 0

| CMP || B || W || L || Compare || (Destination) - (Source) || – || * || * || * || *

| CMPA || || W || L || Compare Address || (Destination) - (Source) || – || * || * || * || *

| CMPI || B || W || L || Compare Immediate || (Destination) - Immediate Data || – || * || * || * || *

| CMPM || B || W || L || Compare Memory || (Destination) - (Source) || – || * || * || * || *

| DBcc || || W || || Test Condition, Decrement and Branch || If ~cc then Dn - 1 → Dn; if Dn ≠ -1 then PC + d → PC || – || – || – || – || –

| DIVS || || W || || Signed Divide || (Destination) / (Source) → Destination || – || * || * || * || 0

| DIVU || || W || || Unsigned Divide || (Destination) / (Source) → Destination || – || * || * || * || 0

| EOR || B || W || L || Exclusive OR Logical || (Destination) ⊕ (Source) → Destination || – || * || * || 0 || 0

| EORI || B || W || L || Exclusive OR Immediate || (Destination) ⊕ Immediate Data → Destination || – || * || * || 0 || 0

| EORI to CCR || B || || || Exclusive OR Immediate to Condition Codes || (Source) ⊕ CCR → CCR || * || * || * || * || *

| EORI to SR || || W || || Exclusive OR Immediate to Status Register || (Source) ⊕ SR → SR || * || * || * || * || *

| EXG || || || L || Exchange Register || Rx ↔ Ry || – || – || – || – || –

| EXT || || W || L || Sign Extend || (Destination) Sign-Extended → Destination || – || * || * || 0 || 0

| JMP || || || || Jump || Destination → PC || – || – || – || – || –

| JSR || || || || Jump to Subroutine || PC → (SP); Destination → PC || – || – || – || – || –

| LEA || || || L || Load Effective Address || < ea > → An || – || – || – || – || –

| LINK || || || || Link and Allocate || An → (SP); SP → An; SP + Displacement → SP || – || – || – || – || –

| LSL, LSR || B || W || L || Logical Shift || (Destination) Shifted by < count > → Destination || * || * || * || 0 || *

| MOVE || B || W || L || Move Data from Source to Destination || (Source) → Destination || – || * || * || 0 || 0

| MOVE to CCR || || W || || Move to Condition Code || (Source) → CCR || * || * || * || * || *

| MOVE to SR || || W || || Move to Status Register || (Source) → SR || * || * || * || * || *

| MOVE from SR || || W || || Move from the Status Register || SR → Destination || – || – || – || – || –

| MOVE USP || || || L || Move User Stack Pointer || USP → An; An → USP || – || – || – || – || –

| MOVEA || || W || L || Move Address || (Source) → Destination || – || – || – || – || –

| MOVEM || || W || L || Move Multiple Registers || Registers → Destination

| MOVEP || || W || L || Move Peripheral Data || (Source) → Destination || – || – || – || – || –

| MOVEQ || || || L || Move Quick || Immediate Data → Destination || – || * || * || 0 || 0

| MULS || || W || || Signed Multiply || (Destination) × (Source) → Destination || – || * || * || 0 || 0

| MULU || || W || || Unsigned Multiply || (Destination) × (Source) → Destination || – || * || * || 0 || 0

| NBCD || B || || || Negate Decimal with Extend || -((Destination)⏨ - X) → Destination || * || U || * || U || *

| NEG || B || W || L || Negate || 0 - (Destination) → Destination || * || * || * || * || *

| NEGX || B || W || L || Negate with Extend || 0 - (Destination) - X → Destination || * || * || * || * || *

| NOP || || || || No Operation || – || – || – || – || – || –

| NOT || B || W || L || Logical Complement || ~(Destination) → Destination || – || * || * || 0 || 0

| OR || B || W || L || Inclusive OR Logical || (Destination) ∨ (Source) → Destination || – || * || * || 0 || 0

| ORI || B || W || L || Inclusive OR Immediate || (Destination) ∨ Immediate Data → Destination || – || * || * || 0 || 0

| ORI to CCR || B || || || Inclusive OR Immediate to Condition Codes || (Source) ∨ CCR → CCR || * || * || * || * || *

| ORI to SR || || W || || Inclusive OR Immediate to Status Register || (Source) ∨ SR → SR || * || * || * || * || *

| PEA || || || L || Push Effective Address || < ea > → (SP) || – || – || – || – || –

| RESET || || || || Reset External Device || – || – || – || – || – || –

| ROL, ROR || B || W || L || Rotate (Without Extend) || (Destination) Rotated by < count > → Destination || – || * || * || 0 || *

| ROXL, ROXR || B || W || L || Rotate with Extend || (Destination) Rotated by < count > → Destination || * || * || * || 0 || *

| RTE || || || || Return from Exception || (SP) → SR; (SP) → PC || * || * || * || * || *

| RTR || || || || Return and Restore Condition Codes || (SP) → CC; (SP) → PC || * || * || * || * || *

| RTS || || || || Return from Subroutine || (SP) → PC || – || – || – || – || –

| SBCD || B || || || Subtract Decimal with Extend || (Destination)⏨ - (Source)⏨ - X → Destination || * || U || * || U || *

| Scc || B || || || Set According to Condition || If cc then 1’s → Destination else 0’s → Destination || – || – || – || – || –

| STOP || || W || || Load Status Register and Stop || Immediate Data → SR; STOP || * || * || * || * || *

| SUB || B || W || L || Subtract Binary || (Destination) - (Source) → Destination || * || * || * || * || *

| SUBA || || W || L || Subtract Address || (Destination) - (Source) → Destination || – || – || – || – || –

| SUBI || B || W || L || Subtract Immediate || (Destination) - Immediate Data → Destination || * || * || * || * || *

| SUBQ || B || W || L || Subtract Quick || (Destination) - Immediate Data → Destination || * || * || * || * || *

| SUBX || B || W || L || Subtract with Extend || (Destination) - (Source) - X → Destination || * || * || * || * || *

| SWAP || || W || || Swap Register Halves || Register [31:16] ↔ Register [15:0] || – || * || * || 0 || 0

| TAS || B || || || Test and Set an Operand || (Destination) Tested → CC; 1 → [7] OF Destination || – || * || * || 0 || 0

| TRAP || || || || Trap || PC → (SSP); SR → (SSP); (Vector) → PC || – || – || – || – || –

| TRAPV || || || || Trap on Overflow || If V then TRAP || – || – || – || – || –

| TST || B || W || L || Test an Operand || (Destination) Tested → CC || – || * || * || 0 || 0

| UNLK || || || || Unlink || An → SP; (SP) → An || – || – || – || – || –

=Block Diagram = [[File:68000-die-blocks.jpg|400px]] <br> = CPU Pinout ==

*[https://wwwyoutu.computerhistory.orgbe/collections/oralhistories/ Oral history collection]: [https://www.computerhistory.org/collections/catalog/102658164 UaHtGf4aRLs Motorola 68000oral history panel]