[[File:Motorola 68000 CPU.jpg|thumb|right|68000 CPU in plastic, ceramic and PLCC versions]]
The [[Motorola 68000]] (commonly abbreviated as 68k) is a landmark microprocessor introduced in 1979 by Motorola Semiconductor.
Although there were definitely other CPUs in use in the 1980s, the vast majority of microcomputers people had at home or at the office used either a [[MOS 6502]] (or one of its variants), a Zilog [[Z80]], an early member of the [[Intel 8086]] family, or a [[Motorola 68000]].
Among those four CPUs, the 68000 is the easiest to program in assembly due to its clean, orthogonal 32-bit instruction set and linear memory model.
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The microcode is a series of pointers into assorted microsubroutines in the nanocode. The nanocode performs the actual routing and selecting of registers and functions, and directs results. Decoding of an instruction's op code generates starting addresses in the microcode for the type of operation and the addressing mode. [http://www.easy68k.com/paulrsm/doc/dpbm68k1.htm Source]
See: [https://gendev.spritesmind.net/forum/viewtopic.php?t=3023 Tech topic about a microcode-level 68000 core] [https://www.atari-forum.com/viewtopic.php?t=42568 New 68k core in mame] [https://og.kervella.org/m68k/ Motorola 68000 microcode]
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== Register Structure File ==
The 68000’s register file is one of its most celebrated features. It provides{| class="wikitable" style="white-space:nowrap;"* ! Register !! Size !! Description !! Notes|-| D0 - D7 || 32-bit || Data Registers (D0–D7): These are 32 bits wide and are used for general|| General-purpose registers for data manipulation (arithmetic and logical operations. However, when operating on logic). Can be accessed as 8-bit (byte or , `.B`), 16-bit (word data, only the lower 8 `.W`), or 16 bits are affected32-bit (long word, `.L`). Not typically used directly for memory addressing.* |-| A0 - A6 || 32-bit || Address Registers (A0–A7): Also 32 bits wide, these || General-purpose registers are primarily used as pointers or index registers for pointer operations and memory addressing modes. A7 doubles as the stack pointer Can be used for some 16-bit/32-bit arithmetic (SPoperations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.* Status Register |-| A7 (SRSP/USP/SSP)|| 32-bit || Stack Pointer || Two physically separate registers exist: This 16‑bit register comprises an 8‑bit system byte User Stack Pointer (accessible only in supervisor modeUSP) and an 8‑bit user byte known as the condition code register Supervisor Stack Pointer (CCRSSP).**The CCR contains processor uses the standard flags—zero active one based on the S-bit (ZSupervisor state)in the Status Register.Used implicitly by stack operations (`PEA`, carry `LINK`, `UNLK`, `MOVE to/from -(CAn), overflow /(VAn)+`), negative subroutine calls (N`JSR`, `BSR`), and extend returns (X`RTS`, `RTR`), and exceptions.**The 3 least significant bits |-| PC (bits 8, 9 and 10Program Counter) || 32-bit || Points to the address of the Status register’s System byte form the interrupt mask. The interrupt priorities are numbered from 1 next instruction to 7, with level 7 having the highest priority. The level 7 interrupt is nonmaskable and thus cannot be disabledfetched.**Bit 13 of the status register is the S flag|| Although 32-bit internally, which specifies whether the MC68000 is in supervisor mode or user modeoriginal 68000 had a 24-bit address bus (16MB addressable space).**Bit 15 of the status register is the T flag, which specifies whether the MC68000 is in trace modeLater variants (68010+) used more address lines. After each instruction is executed in the trace modeModified by branches, jumps, calls, a trap is forced so that a debugging program can monitor the results of that instruction’s executionreturns, exceptions.|-<br> == Operating Modes == Two distinct operating modes are available with the 68000 | SR (Status Register) || 16-bit || Holds processor to protect the operating status (Condition Codes) and system from user programscontrol bits. The two modes are called user mode, Divided into User Byte (CCR) and supervisor modeSystem Byte. A flag in the status register will determine which state the processor is in at any one time. Certain instructions <br/> '''User Byte (e.g.CCR - Condition Code Register, STOPbits 0-7) cannot be executed while the 68000 is in user mode:''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10, and a privilege violation exception process will be initiated by the processor if such an execution is attempted. When the processor is in user mode9, the user stack pointer 8 - I2, I1, I0 (USPInterrupt Mask) will be used by stack related operations. Conversely, the supervisor stack pointer <br/> * bit 13 - S (SSPSupervisor State) will be used when the processor is <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in supervisor modebase 68000) || User programs can typically only read/write the CCR (lower byte). System Byte modification requires Supervisor privileges. The two stack pointers are also treated as address registers, X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and are both labelled active A7).T bit enables single-step tracing. I bits control interrupt priority level.|}
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== Instruction Set ==
The Motorola 68000 was renowned for its rich, orthogonal instruction set:
{| class="wikitable"
|+ 68000 Instruction Set Table
! rowspan=2|Mnemonic !! colspan="3" | Size !! rowspan=2|Description !! rowspan=2|Operation !! colspan="5" | Condition Codes
|-
! B !! W !! L !! X !! N !! Z !! V !! C
|-
| ABCD || B || || || Add Decimal with Extend || (Destination)⏨ + (Source)⏨ + X → Destination || * || U || * || U || *
|-
| ADD || B || W || L || Add Binary || (Destination) + (Source) → Destination || * || * || * || * || *
|-
| ADDA || || W || L || Add Address || (Destination) + (Source) → Destination || – || – || – || – || –
|-
| ADDI || B || W || L || Add Immediate || (Destination) + Immediate Data → Destination || * || * || * || * || *
|-
| ADDQ || B || W || L || Add Quick || (Destination) + Immediate Data → Destination || * || * || * || * || *
|-
| ADDX || B || W || L || Add Extended || (Destination) + (Source) + X → Destination || * || * || * || * || *
|-
| AND || B || W || L || AND Logical || (Destination) ∧ (Source) → Destination || – || * || * || 0 || 0
|-
| ANDI || B || W || L || AND Immediate || (Destination) ∧ Immediate Data → Destination || – || * || * || 0 || 0
|-
| ANDI to CCR || B || || || AND Immediate to Condition Codes || (Source) ∧ CCR → CCR || * || * || * || * || *
|-
| ANDI to SR || || W || || AND Immediate to Status Register || (Source) ∧ SR → SR || * || * || * || * || *
|-
| ASL, ASR || B || W || L || Arithmetic Shift || (Destination) Shifted by < count > → Destination || * || * || * || * || *
|-
| Bcc || || || || Branch Conditionally || If cc then PC + d → PC || – || – || – || – || –
|-
| BCHG || B || || L || Test a Bit and Change || ~(< bit number >) OF Destination → Z
~(< bit number >) OF Destination → < bit number > OF Destination
|| – || – || * || – || –
|-
| BCLR || B || || L || Test a Bit and Clear || ~(< bit number >) OF Destination → Z
0 → < bit number > OF Destination
|| – || – || * || – || –
|-
| BRA || || || || Branch Always || PC + d → PC || – || – || – || – || –
|-
| BSET || B || || L || Test a Bit and Set || ~(< bit number >) OF Destination → Z
1 → < bit number > OF Destination
|| – || – || * || – || –
|-
| BSR || || || || Branch to Subroutine || PC → (SP); PC + d → PC || – || – || – || – || –
|-
| BTST || B || || L || Test a Bit || ~(< bit number >) OF Destination → Z || – || – || * || – || –
|-
| CHK || || W || || Check Register Against Bounds || If Dn < 0 or Dn > (ea) then TRAP || – || * || U || U || U
|-
| CLR || B || W || L || Clear Operand || 0 → Destination || – || 0 || 1 || 0 || 0
|-
| CMP || B || W || L || Compare || (Destination) - (Source) || – || * || * || * || *
|-
| CMPA || || W || L || Compare Address || (Destination) - (Source) || – || * || * || * || *
|-
| CMPI || B || W || L || Compare Immediate || (Destination) - Immediate Data || – || * || * || * || *
|-
| CMPM || B || W || L || Compare Memory || (Destination) - (Source) || – || * || * || * || *
|-
| DBcc || || W || || Test Condition, Decrement and Branch || If ~cc then Dn - 1 → Dn; if Dn ≠ -1 then PC + d → PC || – || – || – || – || –
|-
| DIVS || || W || || Signed Divide || (Destination) / (Source) → Destination || – || * || * || * || 0
|-
| DIVU || || W || || Unsigned Divide || (Destination) / (Source) → Destination || – || * || * || * || 0
|-
| EOR || B || W || L || Exclusive OR Logical || (Destination) ⊕ (Source) → Destination || – || * || * || 0 || 0
|-
| EORI || B || W || L || Exclusive OR Immediate || (Destination) ⊕ Immediate Data → Destination || – || * || * || 0 || 0
|-
| EORI to CCR || B || || || Exclusive OR Immediate to Condition Codes || (Source) ⊕ CCR → CCR || * || * || * || * || *
|-
| EORI to SR || || W || || Exclusive OR Immediate to Status Register || (Source) ⊕ SR → SR || * || * || * || * || *
|-
| EXG || || || L || Exchange Register || Rx ↔ Ry || – || – || – || – || –
|-
| EXT || || W || L || Sign Extend || (Destination) Sign-Extended → Destination || – || * || * || 0 || 0
|-
| JMP || || || || Jump || Destination → PC || – || – || – || – || –
|-
| JSR || || || || Jump to Subroutine || PC → (SP); Destination → PC || – || – || – || – || –
|-
| LEA || || || L || Load Effective Address || < ea > → An || – || – || – || – || –
|-
| LINK || || || || Link and Allocate || An → (SP); SP → An; SP + Displacement → SP || – || – || – || – || –
|-
| LSL, LSR || B || W || L || Logical Shift || (Destination) Shifted by < count > → Destination || * || * || * || 0 || *
|-
| MOVE || B || W || L || Move Data from Source to Destination || (Source) → Destination || – || * || * || 0 || 0
|-
| MOVE to CCR || || W || || Move to Condition Code || (Source) → CCR || * || * || * || * || *
|-
| MOVE to SR || || W || || Move to Status Register || (Source) → SR || * || * || * || * || *
|-
| MOVE from SR || || W || || Move from the Status Register || SR → Destination || – || – || – || – || –
|-
| MOVE USP || || || L || Move User Stack Pointer || USP → An; An → USP || – || – || – || – || –
|-
| MOVEA || || W || L || Move Address || (Source) → Destination || – || – || – || – || –
|-
| MOVEM || || W || L || Move Multiple Registers || Registers → Destination
(Source) → Registers
|| – || – || – || – || –
|-
| MOVEP || || W || L || Move Peripheral Data || (Source) → Destination || – || – || – || – || –
|-
| MOVEQ || || || L || Move Quick || Immediate Data → Destination || – || * || * || 0 || 0
|-
| MULS || || W || || Signed Multiply || (Destination) × (Source) → Destination || – || * || * || 0 || 0
|-
| MULU || || W || || Unsigned Multiply || (Destination) × (Source) → Destination || – || * || * || 0 || 0
|-
| NBCD || B || || || Negate Decimal with Extend || -((Destination)⏨ - X) → Destination || * || U || * || U || *
|-
| NEG || B || W || L || Negate || 0 - (Destination) → Destination || * || * || * || * || *
|-
| NEGX || B || W || L || Negate with Extend || 0 - (Destination) - X → Destination || * || * || * || * || *
|-
| NOP || || || || No Operation || – || – || – || – || – || –
|-
| NOT || B || W || L || Logical Complement || ~(Destination) → Destination || – || * || * || 0 || 0
|-
| OR || B || W || L || Inclusive OR Logical || (Destination) ∨ (Source) → Destination || – || * || * || 0 || 0
|-
| ORI || B || W || L || Inclusive OR Immediate || (Destination) ∨ Immediate Data → Destination || – || * || * || 0 || 0
|-
| ORI to CCR || B || || || Inclusive OR Immediate to Condition Codes || (Source) ∨ CCR → CCR || * || * || * || * || *
|-
| ORI to SR || || W || || Inclusive OR Immediate to Status Register || (Source) ∨ SR → SR || * || * || * || * || *
|-
| PEA || || || L || Push Effective Address || < ea > → (SP) || – || – || – || – || –
|-
| RESET || || || || Reset External Device || – || – || – || – || – || –
|-
| ROL, ROR || B || W || L || Rotate (Without Extend) || (Destination) Rotated by < count > → Destination || – || * || * || 0 || *
|-
| ROXL, ROXR || B || W || L || Rotate with Extend || (Destination) Rotated by < count > → Destination || * || * || * || 0 || *
|-
| RTE || || || || Return from Exception || (SP) → SR; (SP) → PC || * || * || * || * || *
|-
| RTR || || || || Return and Restore Condition Codes || (SP) → CC; (SP) → PC || * || * || * || * || *
|-
| RTS || || || || Return from Subroutine || (SP) → PC || – || – || – || – || –
|-
| SBCD || B || || || Subtract Decimal with Extend || (Destination)⏨ - (Source)⏨ - X → Destination || * || U || * || U || *
|-
| Scc || B || || || Set According to Condition || If cc then 1’s → Destination else 0’s → Destination || – || – || – || – || –
|-
| STOP || || W || || Load Status Register and Stop || Immediate Data → SR; STOP || * || * || * || * || *
|-
| SUB || B || W || L || Subtract Binary || (Destination) - (Source) → Destination || * || * || * || * || *
|-
| SUBA || || W || L || Subtract Address || (Destination) - (Source) → Destination || – || – || – || – || –
|-
| SUBI || B || W || L || Subtract Immediate || (Destination) - Immediate Data → Destination || * || * || * || * || *
|-
| SUBQ || B || W || L || Subtract Quick || (Destination) - Immediate Data → Destination || * || * || * || * || *
|-
| SUBX || B || W || L || Subtract with Extend || (Destination) - (Source) - X → Destination || * || * || * || * || *
|-
| SWAP || || W || || Swap Register Halves || Register [31:16] ↔ Register [15:0] || – || * || * || 0 || 0
|-
| TAS || B || || || Test and Set an Operand || (Destination) Tested → CC; 1 → [7] OF Destination || – || * || * || 0 || 0
|-
| TRAP || || || || Trap || PC → (SSP); SR → (SSP); (Vector) → PC || – || – || – || – || –
|-
| TRAPV || || || || Trap on Overflow || If V then TRAP || – || – || – || – || –
|-
| TST || B || W || L || Test an Operand || (Destination) Tested → CC || – || * || * || 0 || 0
|-
| UNLK || || || || Unlink || An → SP; (SP) → An || – || – || – || – || –
|}
* 1: set
* U: undefined
Bcc, DBcc and Scc families of instructions make use of the CCR. The following table lists all the possible conditions we can test:
{| class="wikitable"
! Instruction
! Full name
! Tested condition
! Notes
|-
| CC
| Carry Clear
| C == 0
|
|-
| CS
| Carry Set
| C == 1
|
|-
| EQ
| EQual
| Z == 1
|
|-
| F
| False
| Always false
| Not available for Bcc
|-
| GE
| Greater or Equal
| N == V
|
|-
| GT
| Greater Than
| N == V and Z == 0
|
|-
| HI
| HIgher than
| C == 0 and Z == 0
|
|-
| LE
| Less or Equal
| Z == 1 or N != V
|
|-
| LS
| Lower or Same
| C == 1 or Z == 1
|
|-
| LT
| Less Than
| N != V
|
|-
| MI
| MInus
| N == 1
|
|-
| NE
| Not Equal
| Z == 0
|
|-
| PL
| PLus
| N == 0
|
|-
| T
| True
| Always true
| Not available for Bcc
|-
| VC
| oVerflow Clear
| V == 0
|
|-
| VS
| oVerflow Set
| V == 1
|
|}
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= Floating Point Unit =
Unlike the Intel 8086, the Motorola 68000 lacked native support for an FPU co-processor. This functionality arrived in 1984 with Motorola introduced the 68881 FPUin 1984, which could function as a peripheral alongside the 68000. But it was primarily designed specifically for to integrate seamlessly with the 32-bit 68020 , taking advantage of its co-processorinterface.
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*[https://www.chibiakumas.com/68000/ Learn Assembly Programming with ChibiAkumas] Multi-platform 68000 tutorial
*[http://goldencrystal.free.fr/M68kOpcodes-v2.3.pdf Decoding m68k opcodes]
*[https://wwwyoutu.computerhistory.orgbe/collections/oralhistories/ Oral history collection]: [https://www.computerhistory.org/collections/catalog/102658164 UaHtGf4aRLs Motorola 68000oral history panel]
*[http://www.easy68k.com/paulrsm/doc/dpbm68k1.htm Part 1] [http://www.easy68k.com/paulrsm/doc/dpbm68k2.htm Part 2] [http://www.easy68k.com/paulrsm/doc/dpbm68k3.htm Part 3] Design philosophy behind Motorola's MC68000
*[https://gendev.spritesmind.net/forum/viewtopic.php?t=2925 Full list of 68k patents]