[[File:Motorola 68000 CPU.jpg|thumb|right|68000 CPU in plastic, ceramic and PLCC versions]]
The [[Motorola 68000]] (commonly abbreviated as 68k) is a landmark microprocessor introduced in 1979 by Motorola Semiconductor.
| A0 - A6 || 32-bit || Address Registers || General-purpose registers primarily used as pointers or index registers for memory addressing. Can be used for some 16-bit/32-bit arithmetic (operations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.
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| A7 (SP/USP/SSP) || 32-bit || Stack Pointer || Two physically separate registers exist: User Stack Pointer (USP) and Supervisor Stack Pointer (SSP). The processor uses the active one based on the S-bit (Supervisor state) in the Status Register. Used implicitly by stack operations (`PEA`, `LINK`, `UNLK`, `MOVE to/from -(An)/(An)+`), subroutine calls (`JSR`, `BSR`), returns (`RTS`, `RTR`), and exceptions.
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| PC (Program Counter) || 32-bit || Points to the address of the next instruction to be fetched. || Although 32-bit internally, the original 68000 had a 24-bit address bus (16MB addressable space). Later variants (68010+) used more address lines. Modified by branches, jumps, calls, returns, exceptions.
|-
| SR (Status Register) || 16-bit || Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7):''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10,9,8 - I2, I1, I0 (Interrupt Mask) <br/> * bit 13 - S (Supervisor State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) || User programs can typically only read/write the CCR (lower byte). System Byte modification requires Supervisor privileges. X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and active A7). T bit enables single-step tracing. I bits control interrupt priority level.
|}
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== Operating Modes == Two distinct operating modes are available with the 68000 processor to protect the operating system from user programs. The two modes are called user mode, and supervisor mode. A flag in the status register will determine which state the processor is in at any one time. Certain instructions (e.g., STOP) cannot be executed while the 68000 is in user mode, and a privilege violation exception process will be initiated by the processor if such an execution is attempted. When the processor is in user mode, the user stack pointer (USP) will be used by stack related operations. Conversely, the supervisor stack pointer (SSP) will be used when the processor is in supervisor mode. The two stack pointers are also treated as address registers, and are both labelled A7. <br> == Instruction Set ==
The Motorola 68000 was renowned for its rich, orthogonal instruction set:
* 1: set
* U: undefined
Bcc, DBcc and Scc families of instructions make use of the CCR. The following table lists all the possible conditions we can test:
{| class="wikitable"
! Instruction
! Full name
! Tested condition
! Notes
|-
| CC
| Carry Clear
| C == 0
|
|-
| CS
| Carry Set
| C == 1
|
|-
| EQ
| EQual
| Z == 1
|
|-
| F
| False
| Always false
| Not available for Bcc
|-
| GE
| Greater or Equal
| N == V
|
|-
| GT
| Greater Than
| N == V and Z == 0
|
|-
| HI
| HIgher than
| C == 0 and Z == 0
|
|-
| LE
| Less or Equal
| Z == 1 or N != V
|
|-
| LS
| Lower or Same
| C == 1 or Z == 1
|
|-
| LT
| Less Than
| N != V
|
|-
| MI
| MInus
| N == 1
|
|-
| NE
| Not Equal
| Z == 0
|
|-
| PL
| PLus
| N == 0
|
|-
| T
| True
| Always true
| Not available for Bcc
|-
| VC
| oVerflow Clear
| V == 0
|
|-
| VS
| oVerflow Set
| V == 1
|
|}
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