Changes
Used in standard RS232 interfaces for the CPC([[Amstrad_Serial_Interface]]), mapped to following Ports:
FADCh Amstrad RS323 Z8470 (Z80 DART) Channel A Data (R/W)
Control/Status Registers
In the default state, reads/writes on the Control/Status port are accessing the RR0/WR0 registers. After writing a non-zero index value "n" to Bit0-2 of WR0, the next read/write operation on the Control/Status port will access the corresponding RRn/WRn register.
== Control Registers ==
WR0 Write register 0
0-7 DART: N/A, SIO: MSBs of 16bit sync char, or SDLC flag (should be 7Eh)
== Status Registers ==
RR0 Read register 0 (General Status Bits)
- Reserved / don't use
== Data Registers ==
Rx Data Register
has a 1-stage FIFO, plus 1 tx shift register (2-stages in total)
Interrupts can occur on both channel A and channel B, certain bits (like
