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8253 chip

1,249 bytes added, 23:41, 16 December 2010
8253 and 8254 are basically the same: both are pin-compatible and software compatible. The difference is that the 8254 supports higher clock frequencies, and it includes a readback feature for the control registers (which are write-only on 8253).
 
== Registers ==
 
=== Timer Registers ===
 
* 8253/8254 Timer 0 Register (R/W)
* 8253/8254 Timer 1 Register (R/W)
* 8253/8254 Timer 2 Register (R/W)
These ports allow to access three decrementing 16bit timers. Assuming that the corresponding Control Registers are set to "LSB-then-MSB", the 16bit reload values (aka divider values) are written in two 8bit fractions:
 
1st write: LSB of reload value
2nd write: MSB of reload value
 
For the CPC RS232 interfaces, the baudrates are calculated as such:
 
Baudrate = 2MHz / reload / prescaler
 
Where "prescaler" is an additional divider in the DART or 6850 chip. Eg.
 
300 baud = 2MHz / 01A0h / 16
9600 baud = 2MHz / 000Dh / 16
 
Note: Reading from the Timer registers does probably return the current counter values rather than the reload value (?) also not sure if/how it freezes between LSB and MSB reads, and how Control bits 4-5 are working exactly.
 
=== Control Registers ===
 
* 8253/8254 Timer 0-2 Control Registers (W)
This port allows to configure three write-only 6bit registers: Bit6-7 specify which of the registers is to be updated, Bit0-5 contain the new value for that register.
 
7-6 Counter Number (0..2=Counter 0..2, and 8253: 3=Reserved, or 8254: 3=Readback)
5-4 Read/Load (0=Latching?, 1=LSB only, 2=MSB only, 3=LSB-then-MSB)
3-1 Mode
0=Interrupt on Terminal Count
1=Programmable One-Shot
2=Rate Generator (short edge, low for 1 period of input clock)
3=Rate Generator (square wave, low for 2nd half of counter range)
4=Software Triggered Strobe
5=Hardware Triggered Strobe
6=Same as Mode 2
7=Same as Mode 3
0 BCD (0=normal, 1=bcd)
 
When used as RS232 Baudrate Generator (ie. as in the CPC), all three registers should be set to square-wave non-bcd lsb-then-msb (ie. write values 36h, 76h, and B6h to this port).
== Usage in CPC interfaces ==
Clock Input seems to be 2MHz, Clock output goes to a [[Z80-DART/Z80-SIO chip]],
Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip
 
=== MHT Ingenieros RS232 para Amstrad ===
Used by [[RS-232 para Amstrad]] from MHT Ingenieros, mapped to Ports:
FBDCh - MHT RS232 8253 timer 0 (transmit baudrate)
FBDDh - MHT RS232 8253 timer 1 (receive baudrate)
FBDEh - MHT RS232 8253 timer 2 (used as 1ms timer)
FBDFh - MHT RS232 8253 timer 0-2 control
Clock Input is '''unknown''', Clock output goes to a [[8251 USART chip]],
Clock Output may be further divided by 1, 16, or 64 in the USART chip
 
=== Schneiderware V/24 Interface ===
Used by [[Schneiderware V/24 Interface]], mapped to ports:
F9ECh (or F9E8h) Schneiderware V/24 8253 chip Timer 0 (TX clock)
F9EDh (or F9E9h) Schneiderware V/24 8253 chip Timer 1 (RX clock)
F9EEh (or F9EAh) Schneiderware V/24 8253 chip Timer 2 (unused)
F9EFh (or F9EBh) Schneiderware V/24 8253 chip Timer Control
Clock input is jumper select-able: 2MHz (default), or 1MHz.
Clock output goes to a [[8251 USART chip]],
Clock Output may be further divided by 1, 16, or 64 in the USART chip
=== KDS Serial Interface ===
=== Aleste 520EX Serial Interface and Color Palette Swap ===
Also used by [[Aleste 520EX]] CPC clone:
F4X0h Aleste FABCh ExtPort: Forward PPI Port A, to 8253 Baudrate Timer 0 (RX Clock) (W) F4X1h Aleste FABDh ExtPort: Forward PPI Port A, to 8253 Baudrate Timer 1 (TX Clock) (W) F4X2h Aleste FABEh ExtPort: Forward PPI Port A, to 8253 ColorSet Timer 2 (FUTURE) (W) F4X3h Aleste FABFh ExtPort: Forward PPI Port A, to 8253 Timer 0-2 Control Registers (W)
Clock Input for RX/TX is 4MHz, Clock output goes to a [[8251 USART chip]],
Clock Output may be further divided by 1, 16, or 64 in the 8251 chip,
the FUTURE clock is restarted via GATE=[[CRTC]]'s "CURSOR" output,
All registers are write-only (the 8251 chips /RD is wired to VCC)
* Usage: Set PPI Port A data direction must be to output, Aleste ExtReg must enable access . Write Data to 8253PPI Port A (F4XXh), and disable access then set/clear the CS53 bit with two writes to PSGPort (FABCh+n), where n is the 8253 register index.
* Note: According to the Aleste schematic, clock input is 4MHZ (16MHZ/4), and it uses a russian 8253 clone. Not sure if that is correct...? Theoretically the 8253 supports only max 2.6MHZ, and anything faster requires a 8254, not a 8253.
F9DAh Magic Sound Board - 1st 8254 - Timer 2 (DMA Channel 2) (W)
F9DBh Magic Sound Board - 1st 8254 - Timer 0-2 Control (W)
 == Timer Registers == * 8253/8254 Timer 0 Register (R/W)* 8253/8254 Timer 1 Register (R/W)* 8253/8254 Timer 2 Register (R/W)These ports allow to access three decrementing 16bit Clock source for all six timers. Assuming that the corresponding Control Registers are set to "LSB-then-MSB", the 16bit reload values is (aka divider valuesinverted) are written in two 8bit fractions:  1st write: LSB of reload value 2nd write: MSB of reload value For the CPC RS232 interfaces, the baudrates are calculated as such:  Baudrate = 2MHz / reload / prescaler Where "prescaler" is an additional divider in the DART or 6850 chip. Eg.  300 baud = 2MHz / 01A0h / 16 9600 baud = 2MHz / 000Dh / 16 Note: Reading 4MHz from the Timer registers does probably return the current counter values rather than the reload value (?) also not sure if/how it freezes between LSB and MSB reads, and how Control bits 4-5 are working exactly. == Control Registers == 8253 Timer 0-2 Control Registers (W)This expansion port allows to configure three write-only 6bit registers: Bit6-7 specify which of the registers is to be updated, Bit0-5 contain the new value for that register.  7-6 Counter Number (0..2=Counter 0..2, 3=Reserved) 5-4 Read/Load (0=Latching?, 1=LSB only, 2=MSB only, 3=LSB-then-MSB) 3-1 Mode 0=Interrupt on Terminal Count 1=Programmable One-Shot 2=Rate Generator (short edge, low for 1 period of input clock) 3=Rate Generator (square wave, low for 2nd half of counter range) 4=Software Triggered Strobe 5=Hardware Triggered Strobe 6=Same as Mode 2 7=Same as Mode 3 0 BCD (0=normal, 1=bcd) When used as RS232 Baudrate Generator (ie. as in the CPC), all three registers should be set to square-wave non-bcd lsb-then-msb (ie. write values 36h, 76h, and B6h to this port).
== Datasheets ==
* [[Media:8253.pdf]] - 8253 Datasheet (slower clock, write-only control registers)
* [[Media:8254.pdf]] - 8254 Datasheet (faster clock, read/write-able control registers)
 
[[Category:Electronic Component]]
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