Changes
/* Clock sequence */
It seems also better (to create each CLK and not(CLK) from DCM) in order to solve the "magic" ramb16_s16_s16 component time equations (two differents clocks in entry of this component are making a certain clock equation solved automatically by common DCM - smaller common divisor)
Clock sequence was in fact out of law (but running fine in my first versions of FPGAmstrad as I a good blind developer), just think about that a "not" component in clock is out of law... destroying "time constraint" solver (the one telling you when your code is bad (can be better))
=== How to tickle JavaCPC ===
