Changes
/* Interrupt Notes */
Used in standard RS232 interfaces for the CPC ([[Amstrad Serial Interface]]), mapped to following Ports:
FADCh Amstrad RS323 Z8470 (Z80 DART) Channel A Data (R/W)
FADDh Amstrad RS323 Z8470 (Z80 DART) Channel A Control/Status (R/W)
FADFh Amstrad RS323 Z8470 (Z80 DART) Channel B Control/Status (R/W)
Also used by [[Z80-SIO dual ports RS232 interface for CPC (French)]], mapped to: FC7Ch Z80 SIO Channel A Data FC7Dh Z80 SIO Channel A Control/Status FC7Eh Z80 SIO Channel B Data FC7Fh Z80 SIO Channel B Control/Status == Chip Variants (DART, SIO/0, SIO/1, SIO/2, SIO/3, SIO/4)==
Most CPC interfaces should contain the DART chips. Eventually some might use the SIO chips (which are including some additional features).
Note: Five different variants of the SIO chips exist: types 0/1/2 are 40pin DIP chips with slightly different features/pinouts, types 3 (QFP package) and 4 (PLCC package) are 44pin chips, both combining all features of the three 40pin chips.
== Control/Status Registers==
In the default state, reads/writes on the Control/Status port are accessing the RR0/WR0 registers. After writing a non-zero index value "n" to Bit0-2 of WR0, the next read/write operation on the Control/Status port will access the corresponding RRn/WRn register.
== Control Registers ==
WR0 Write register 0
0=No action
1=DART: Reserved, SIO: Reset Receive CRC Checker
2=DART: Reserved, SIO: Reset Transmit CRC Generator
3=DART: Reserved, SIO: Reset Tx Underrun/End of Message latch
2=SDLC Mode (0111 1110 Flag) (SIO only, not DART)
3=External SYNC Mode (SIO only, not DART)
6-7 Rx/Tx DART clock mode (0..3=X1, X16, X32, X64)
0-7 DART: N/A, SIO: MSBs of 16bit sync char, or SDLC flag (should be 7Eh)
== Status Registers ==
RR0 Read register 0 (General Status Bits)
- Reserved / don't use
== Data Registers ==
Rx Data Register
has a 1-stage FIFO, plus 1 tx shift register (2-stages in total)
Interrupts can occur on both channel A and channel B, certain bits (like
the interrupt pending flag can be read via RR0.Bit1 of channel A only