Changes
/* Interrupt Notes */
Used in standard RS232 interfaces for the CPC ([[Amstrad Serial Interface]]), mapped to following Ports:
FADCh Amstrad RS323 Z8470 (Z80 DART) Channel A Data (R/W)
FADDh Amstrad RS323 Z8470 (Z80 DART) Channel A Control/Status (R/W)
FADFh Amstrad RS323 Z8470 (Z80 DART) Channel B Control/Status (R/W)
Also used by [[Z80-SIO dual ports RS232 interface for CPC (French)]], mapped to: FC7Ch Z80 SIO Channel A Data FC7Dh Z80 SIO Channel A Control/Status FC7Eh Z80 SIO Channel B Data FC7Fh Z80 SIO Channel B Control/Status == Chip Variants (DART, SIO/0, SIO/1, SIO/2, SIO/3, SIO/4)==
Most CPC interfaces should contain the DART chips. Eventually some might use the SIO chips (which are including some additional features).
Note: Five different variants of the SIO chips exist: types 0/1/2 are 40pin DIP chips with slightly different features/pinouts, types 3 (QFP package) and 4 (PLCC package) are 44pin chips, both combining all features of the three 40pin chips.
== Control/Status Registers==
In the default state, reads/writes on the Control/Status port are accessing the RR0/WR0 registers. After writing a non-zero index value "n" to Bit0-2 of WR0, the next read/write operation on the Control/Status port will access the corresponding RRn/WRn register.
the interrupt pending flag can be read via RR0.Bit1 of channel A only
